Douglas S Larson

US Patent:

6349376, Feb 19, 2002

Filed:

Jul 7, 1998

Appl. No.:

09/111243

Inventors:

Douglas Alan Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Bosie ID

International Classification:

G06F 1206

US Classification:

711211, 711209, 36523006, 365233

Abstract:

A method for providing the results of an address decode operation involves comparing the address of an address to be decoded with the address range containing an address previously decoded in a previous address decode operation, selecting the results of the previous address decode operation if the address of an address to be decoded is within the address range containing an address previously decoded in a previous address decode operation, and decoding the address to be decoded in a current address decode operation and selecting the results of the current address decode operation if the address containing an address to be decoded is not within the address range of an address previously decoded in a previous address decode operation.

US Patent:

6363446, Mar 26, 2002

Filed:

Jun 12, 1999

Appl. No.:

09/332278

Inventors:

Douglas A. Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1336

US Classification:

710113, 710107, 710110, 710116, 710119, 710240

Abstract:

One embodiment of the present invention provides a method for selectively encoding bus grant lines to reduce I/O pin requirements. The method includes receiving a number of grant lines emanating from a bus arbitration circuit and encoding the grant lines into a smaller number of encoded grant lines. The method selects outputs from between the encoded grant lines and a first subset of the grant lines. These outputs are driven off of a semiconductor chip through a number of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the output pins. During a second mode of operation, the encoded grant lines are selected to driven through the output pins. In a variation on the above embodiment, the method additionally receives a number of bus request lines. These request lines are divided into a first subset and a second subset.

US Patent:

6363447, Mar 26, 2002

Filed:

Jun 12, 1999

Appl. No.:

09/332279

Inventors:

Douglas A. Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1336

US Classification:

710113, 710107, 710110, 710116, 710119, 710240

Abstract:

One embodiment of the present invention provides an apparatus that selectively encodes bus grant lines to reduce I/O pin requirements. This apparatus includes a semiconductor chip with bus arbitration circuit. A number of grant lines emanate from the bus arbitration circuit. An encoder circuit encodes the grant lines into a smaller number of encoded grant lines. A selector circuit selects outputs from between the encoded grant lines and a first subset of grant lines. These outputs pass through output pins off of the semiconductor chip. During a first mode of operation, the first subset of grant lines is driven through the plurality of output pins. During a second mode of operation, the encoded grant lines are driven through the output pins. A variation on the above embodiment includes a number of bus request lines, which are divided into a first subset and a second subset. The first subset of request lines feeds through a number of input pins into the bus arbitration circuit.

US Patent:

6370593, Apr 9, 2002

Filed:

Feb 4, 1999

Appl. No.:

09/244598

Inventors:

Douglas A. Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710 1, 710 2, 710100

Abstract:

A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.

US Patent:

6385680, May 7, 2002

Filed:

Oct 15, 1999

Appl. No.:

09/418468

Inventors:

Douglas A. Larson - Lakeville MN
Joseph Jeddeloh - Blaine MN
Jeffrey J. Rooney - Blaine MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710119, 710107, 710244, 710240

Abstract:

One embodiment of the present invention provides a method for flexibly allocating I/O pins used for bus grant signals between bus controllers located on a semiconductor chip. The method operates by receiving a first set of grant lines from a first bus arbitration circuit. This first set of grant lines is used to grant control of a first bus to devices on the first bus. The method divides the first set of grant lines into a first subset of grant lines and a second subset of grant lines. The method also receives a second set of grant lines from a second bus arbitration circuit. This second set of grant lines is used to grant control of a second bus to devices on the second bus. The method divides the second set of grant lines into a third subset of grant lines and a fourth subset of grant lines. Next, the method selects outputs from between the first subset of grant lines and the third subset of grant lines, and drives the outputs off of the semiconductor chip through a first set of output pins. During a first mode of operation, the first subset of grant lines is selected to be driven through the first set of output pins, and during a second mode of operation the third subset of grant lines is selected to driven through the first set of output pins.

US Patent:

6389492, May 14, 2002

Filed:

Oct 15, 1999

Appl. No.:

09/418465

Inventors:

Douglas A. Larson - Lakeville MN
Joseph Jeddeloh - NE. Blaine MN
Jeffrey J. Rooney - Blaine MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710107, 710240, 710 52

Abstract:

One embodiment of the present invention provides an apparatus that flexibly allocates I/O pins used for bus grant signals between bus controllers. The apparatus includes a semiconductor chip containing a first bus arbitration circuit and a second bus arbitration circuit. A first set of grant lines originates from the first bus arbitration circuit and is used to grant control of a first bus to devices on the first bus. This first set of grant lines is divided into a first subset of grant lines and a second subset of grant lines. A second set of grant lines originates from the second bus arbitration circuit and is used to grant control of a second bus to devices on the second bus. This second set of grant lines is divided into a third subset of grant lines and a fourth subset of grant lines. A selector circuit selects a plurality of outputs from between the first subset of grant lines and the third subset of grant lines. This plurality of outputs is coupled to a first set of output pins on the semiconductor chip.

US Patent:

6418502, Jul 9, 2002

Filed:

Jun 3, 1999

Appl. No.:

09/324397

Inventors:

Douglas A. Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1300

US Classification:

710306

Abstract:

A circuit to detect when an accelerated graphics port master device terminates a sideband bus data transfer operation The circuit includes a first register to cyclically generate a predetermined sequence of output signals at a rate determined by a first clock signal, a second register to cyclically generate the predetermined sequence of output signals at a rate determined by a second clock signal (each output signal of the second register having a corresponding first register output signal), and a detector to detect a mismatch between an output signal from the second register and a corresponding output signal from the first register.

US Patent:

6430637, Aug 6, 2002

Filed:

Feb 4, 1999

Appl. No.:

09/244371

Inventors:

Douglas A. Larson - Lakeville MN

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G06F 1340

US Classification:

710128, 710 15, 710 27, 710107

Abstract:

A computer system includes a processor/PCI bus bridge that couples a processor bus to a relatively high-speed expansion bus, such as a PCI bus and a PCI extension bus. The PCI extension bus is coupled to a 32-bit PCI device, a 64-bit PCI device, and a non-PCI device, such as a device normally connected to a relatively low speed bus. In operation, an arbiter in the bus bridge selectively grants either the 64-bit PCI device or the non-PCI device access to the PCI extension bus. Data transfers between the processor bus and the non-PCI device can occur simultaneously with data transfers between the processor bus and the 32-bit PCI device. Several non-PCI devices may be coupled to the PCI extension bus. Data transfer between the processor bus and the non-PCI devices may be accomplished alternately if the non-PCI devices share the same lines of the PCI extension bus or simultaneously in the non-PCI devices use different lines of the PCI extension bus.