Douglas W Mercer

US Patent:

6773972, Aug 10, 2004

Filed:

Dec 13, 2001

Appl. No.:

10/023113

Inventors:

Andrew Marshall - Dallas TX
Youngmin Kim - Allen TX
David B Scott - Plano TX
Douglas E. Mercer - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21338

US Classification:

438176, 438181, 438184, 438217, 438231, 438276, 257204, 257288, 257341, 257371

Abstract:

A method of forming a semiconductor circuit ( ). The method forms a first transistor (NT ) using various steps, such as by forming a first source/drain region ( ) as a first doped region in a fixed relationship to a semiconductor substrate ( ) and forming a second source/drain region ( ) as a second doped region in a fixed relationship to the semiconductor substrate. The second doped region and the first doped region are of a same conductivity type. Additionally, the first transistor is formed by forming a first gate ( ) in a fixed relationship to the first source/drain region and the second drain region. The method also forms a second transistor (ST ) using various steps, such as by forming a third source/drain region ( ) as a third doped region in a fixed relationship to the semiconductor substrate and forming a fourth source/drain region ( ) as a fourth doped region in a fixed relationship to the semiconductor substrate. The fourth doped region and the third doped region are of the same conductivity type as the first and second doped regions. Additionally, the second transistor is formed by forming a second gate ( ) in a fixed relationship to the third source/drain region and the fourth drain region.

US Patent:

7045431, May 16, 2006

Filed:

Dec 17, 2003

Appl. No.:

10/738958

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Douglas E. Mercer - Richardson TX, US
Luigi Colombo - Dallas TX, US
Mark Robert Visokay - Richardson TX, US
Haowen Bu - Plano TX, US
Malcolm John Bevan - Dallas TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336

US Classification:

438287, 438303

Abstract:

Methods are disclosed that fabricating semiconductor devices with high-k dielectric layers. The invention removes portions of deposited high-k dielectric layers not below gates and covers exposed portions (e. g. , sidewalls) of high-k dielectric layers during fabrication with an encapsulation layer, which mitigates defects in the high-k dielectric layers and contamination of process tools. The encapsulation layer can also be employed as an etch stop layer and, at least partially, in comprising sidewall spacers. As a result, a semiconductor device can be fabricated with a substantially uniform equivalent oxide thickness.

US Patent:

7208398, Apr 24, 2007

Filed:

Jul 30, 2004

Appl. No.:

10/903805

Inventors:

Peijun J. Chen - Dallas TX, US
Duofeng Yue - Plano TX, US
Douglas E. Mercer - Richardson TX, US
Noel Russell - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/28

US Classification:

438581, 438583, 257E21199

Abstract:

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, halogen atoms () and transition metal atoms () to form a halogen-containing metal layer () on a semiconductor substrate (). The halogen-containing metal layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit () comprising the metal silicide electrode.

US Patent:

7435672, Oct 14, 2008

Filed:

Jul 30, 2004

Appl. No.:

10/903716

Inventors:

Doufeng Yue - Plano TX, US
Noel Russell - Plano TX, US
Peijun J. Chen - Dallas TX, US
Douglas E. Mercer - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/3205

US Classification:

438592, 438652

Abstract:

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, germanium atoms () and transition metal atoms () to form a metal-germanium alloy layer () on a semiconductor substrate (). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

US Patent:

7449385, Nov 11, 2008

Filed:

Jul 26, 2002

Appl. No.:

10/205814

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Luigi Colombo - Dallas TX, US
Douglas E. Mercer - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/336
H01L 21/3205
H01L 21/31

US Classification:

438287, 438591, 438761, 438762, 438778

Abstract:

CMOS gate dielectric made of high-k metal silicates by reaction of metal with silicon dioxide at the silicon surface. Optionally, a silicon dioxide monolayer may be preserved at the interface.

US Patent:

7535066, May 19, 2009

Filed:

Jan 23, 2003

Appl. No.:

10/349686

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Luigi Colombo - Dallas TX, US
Mark R. Visokay - Richardson TX, US
Rajesh Khamankar - Coppell TX, US
Douglas E. Mercer - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 29/76
H01L 29/94

US Classification:

257410, 257411

Abstract:

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.

US Patent:

7803703, Sep 28, 2010

Filed:

Aug 4, 2008

Appl. No.:

12/185189

Inventors:

Doufeng Yue - Plano TX, US
Noel Russell - Plano TX, US
Peijun J. Chen - Dallas TX, US
Douglas E. Mercer - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/3205

US Classification:

438592, 438655, 257E21165

Abstract:

The present invention provides a method of manufacturing a metal silicide electrode () for a semiconductor device (). The method comprises depositing by physical vapor deposition, germanium atoms () and transition metal atoms () to form a metal-germanium alloy layer () on a semiconductor substrate (). The metal-germanium alloy layer and the semiconductor substrate are reacted to form a metal silicide electrode. Other aspects of the present invention include a method of manufacturing an integrated circuit ().

US Patent:

8021990, Sep 20, 2011

Filed:

Apr 9, 2009

Appl. No.:

12/421036

Inventors:

Antonio L. P. Rotondaro - Dallas TX, US
Luigi Colombo - Dallas TX, US
Mark R Visokay - Richardson TX, US
Rajesh Khamankar - Coppell TX, US
Douglas E Mercer - Richardson TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21/31
H01L 21/469

US Classification:

438778, 257E21191, 257E21637, 257E21639, 438216, 438585, 438591, 438783, 438785

Abstract:

A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.