Douglas Mercer

US Patent:

6542099, Apr 1, 2003

Filed:

Nov 21, 2001

Appl. No.:

09/990985

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 333 62, 327395

Abstract:

A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.

US Patent:

6559784, May 6, 2003

Filed:

Nov 21, 2001

Appl. No.:

10/042118

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 327108

Abstract:

A current switching cell for a multi-cell DAC, each cell having a data input and an analog output and including a current switching circuit having a current node; a current definition circuit for providing current to the current switching circuit at the current node; the current definition circuit having a parasitic coupling between the input and the current node; a driver circuit responsive to a data input for actuating the current switching circuit to provide an analog output from the current from the current definition circuit; and a control circuit responsive to at least one common control signal for controlling the current definition circuit and isolating the parasitic coupling between the current node and the common control signal; the driver circuit may also have a parasitic coupling between its driver input and the current node and the control circuit may isolate the parasitic coupling between the current node and the driver input.

US Patent:

6583740, Jun 24, 2003

Filed:

Nov 21, 2001

Appl. No.:

09/990983

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341120, 341136, 327416, 323312

Abstract:

A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

US Patent:

6768438, Jul 27, 2004

Filed:

Jan 24, 2003

Appl. No.:

10/351066

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 327408

Abstract:

Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.

US Patent:

43237959, Apr 6, 1982

Filed:

Feb 12, 1980

Appl. No.:

6/120891

Inventors:

Peter R. Holloway - Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Incorporated - Norwood MA

International Classification:

H03F 3187
H03K 1325

US Classification:

307297

Abstract:

A single-chip 8-bit DAC with bipolar current sources, an output buffer amplifier for developing an output voltage, a regulated reference for producing a calibrated output, and operated by a single-voltage supply, e. g. +5 volts. The buffer amplifier includes means providing for driving the output voltage virtually to ground level when the DAC output is zero. The current sources comprise a single-transistor cell driven by an I. sup. 2 L flip-flop circuit, and the reference supply is merged with the reference transistor circuit regulating the DAC current levels, both aiding in reducing required chip area. A highly efficient bias network is utilized to supply the high-level bias currents required.

US Patent:

54184088, May 23, 1995

Filed:

Jan 7, 1994

Appl. No.:

8/183635

Inventors:

Christopher W. Mangelsdorf - Reading MA
David H. Robertson - Somerville MA
Douglas A. Mercer - Bradford MA
Peter Real - Groveland MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G11C 2702

US Classification:

327 95

Abstract:

A sample-and-hold amplifier in which the held signal is represented as a voltage across a capacitor, but all other signals are represented as currents. At a summing node, the input current and a feedback current are summed to produce a difference current. In the tracking mode, this difference current flows through a closed hold switch onto the input of an integrator. The integrator accumulates the difference current onto the hold capacitor, where it becomes the hold voltage. This hold voltage is converted into a feedback current by a first transconductance amplifier, to provide the negative feedback to the summing node. The hold voltage, which need not equal the input signal, is also applied to the input of a second transconductance amplifier, which provides an output current. The ratio of the two transconductance gains determines the gain accuracy and linearity of the current output. When the hold switch is opened, there is no longer a current path into the hold capacitor, and the output current remains where it was at the moment the switch was opened.