Douglas Derek Mercer

US Patent:

RE37619, Apr 2, 2002

Filed:

Nov 16, 1999

Appl. No.:

09/441319

Inventors:

Douglas A. Mercer - Bradford MA
David H. Robertson - Boxford MA
Ernest T. Stroud - Greensboro NC
David Reynolds - Dove Canyon CA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 32885

US Classification:

341133, 341144, 327 51

Abstract:

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

US Patent:

6674309, Jan 6, 2004

Filed:

Nov 12, 2002

Appl. No.:

10/292114

Inventors:

Douglas A. Mercer - Bradford MA
Michael P. Timko - Andover MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G01R 2500

US Classification:

327 9, 327 94

Abstract:

A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

US Patent:

6738006, May 18, 2004

Filed:

May 6, 2003

Appl. No.:

10/430815

Inventors:

Douglas A. Mercer - Bradford MA
William G. J. Schofield - North Andover MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 341145

Abstract:

A digital to analog converter circuit is segmented into a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit and a sub-digital to analog converting unit including a current source connected to a plurality of cascode units. A cascode bias unit is operatively connected to each cascode unit of the main digital to analog converting unit so as to bias each current source of the main digital to analog converting unit to operate at a same drain voltage. A second cascode bias unit is operatively connected to each cascode unit of the sub-digital to analog converting unit so as to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage. A reference voltage source is operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit. The tying of the reference voltage source to both cascode bias circuits causes the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.

US Patent:

7023255, Apr 4, 2006

Filed:

Jun 23, 2004

Appl. No.:

10/874513

Inventors:

Douglas A. Mercer - Bradford MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 3/356

US Classification:

327199, 327201, 327211, 327212, 327218

Abstract:

A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit. The load compensation circuit provides a first compensation load value upon the clock driver when data at the first and second data inputs is non-changing and provides a second compensation load value relative upon the clock driver when data at the first and second data inputs is changing such that a sum of the first load value and the first compensation load value equals a sum of the second load value and the second compensation load value.

US Patent:

54500842, Sep 12, 1995

Filed:

Aug 12, 1993

Appl. No.:

8/106047

Inventors:

Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Incorporated - Norwood MA

International Classification:

H03M 180

US Classification:

341153

Abstract:

A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementary signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant. Capacitors are included to maintain effectively constant the base voltages of the two switch transistors during the time that the two additional switches are open.

US Patent:

56892578, Nov 18, 1997

Filed:

Jan 5, 1996

Appl. No.:

8/583410

Inventors:

Douglas A. Mercer - Bradford MA
David Reynolds - Georgetown MA
David H. Robertson - Boxford MA
Ernest T. Stroud - Greensboro NC

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 32885

US Classification:

341133

Abstract:

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

US Patent:

6031477, Feb 29, 2000

Filed:

May 7, 1998

Appl. No.:

9/074183

Inventors:

Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144

Abstract:

A differential current switch including a differential switch pair of transistors having first and second complementary control inputs which receive first and second complementary signals so as to be controlled by a control signal with equal delay from a clock signal. A first set of switching transistors is coupled to provide the first complementary signal which controls the first complementary control input of the differential switch pair. A second set of switching transistors is coupled to provide the second complementary signal which controls the second complementary control input of the differential switch pair. First delay transistor pairs are coupled to the complementary outputs of the cross coupled inverter and have the characteristic that the fall times of its outputs are greater than the rise time of its outputs. Second delay transistor pairs are coupled to the first delay transistor pairs and have the characteristic that the rise times of its outputs are greater than the fall times of its outputs. The second delay transistor pairs are coupled to the first and second sets of switching transistors such that a first output of the second delay transistor pairs provides a first input signal to the first set of switching transistor pairs and a second input signal of the second set of switching transistor pairs, and a second output of the second delay transistor pairs provides the second input signal to the first set of switching transistor pairs and the first input signal of the second set of switching transistor pairs.

US Patent:

56126972, Mar 18, 1997

Filed:

Dec 28, 1994

Appl. No.:

8/365300

Inventors:

Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Incorporated - Norwood MA

International Classification:

H03M 180

US Classification:

341153

Abstract:

A digital-to-analog converter including a plurality of binarily-weighted stages each incorporating a differential switch-pair circuit which includes two matched bipolar switch transistors the bases of which are driven by a corresponding pair of complementarry signal sources. Two additional switches are included in this circuit, with each such switch being connected between a respective signal source and its corresponding transistor control electrode. These two switches are both opened before the clock-controlled activation of the complementary signal sources. A short time after such activation, sufficient to assure that the complementary signal voltages have stabilized at their new values, the two additional switches are reclosed simultaneously by a single control signal so as to effect synchronized switchover of the two switch transistors at that instant. Capacitors are included to maintain effectively constant the base voltages of the two switch transistors during the time that the two additional switches are open.