Douglas A Mercer

US Patent:

RE37619, Apr 2, 2002

Filed:

Nov 16, 1999

Appl. No.:

09/441319

Inventors:

Douglas A. Mercer - Bradford MA
David H. Robertson - Boxford MA
Ernest T. Stroud - Greensboro NC
David Reynolds - Dove Canyon CA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 32885

US Classification:

341133, 341144, 327 51

Abstract:

A differential switch accepts a binary control signal and its complement (which may be skewed with respect to the control signal) and latches both signals simultaneously. The latched output signals drive the control terminals of a differential switch pair which connects one of two terminals to a third terminal, depending upon the state of the control terminals. The differential switch may optionally include an inverter which complements the binary control signal, thus eliminating the need for external inversion of the control signal. The switch is particularly applicable for use in a digital to analog converter.

US Patent:

6542099, Apr 1, 2003

Filed:

Nov 21, 2001

Appl. No.:

09/990985

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 333 62, 327395

Abstract:

A method of equalizing total signal delay across a digital to analog interface includes constructing a plurality of unit digital to analog converter cells each having a clock input and a data input and an analog output; constructing an analog output network for summing the analog outputs for delivery to a termination which in combination with the analog output network defines a first predetermined time delay between the unit cells; constructing a clock input distribution network for propagating a clock input to each of the unit cells tapped along the clock input distribution network; and connecting a second termination to the clock input distribution network for establishing the clock input distribution network as a transmission line and defining in combination with the clock input distribution network a second predetermined time interval delay between the clock input to the unit cells equal to the first predetermined in the interval delay for synchronizing the propagation of the clock inputs propagating along the clock input distribution network with the analog outputs propagating along the analog output network.

US Patent:

6559784, May 6, 2003

Filed:

Nov 21, 2001

Appl. No.:

10/042118

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 327108

Abstract:

A current switching cell for a multi-cell DAC, each cell having a data input and an analog output and including a current switching circuit having a current node; a current definition circuit for providing current to the current switching circuit at the current node; the current definition circuit having a parasitic coupling between the input and the current node; a driver circuit responsive to a data input for actuating the current switching circuit to provide an analog output from the current from the current definition circuit; and a control circuit responsive to at least one common control signal for controlling the current definition circuit and isolating the parasitic coupling between the current node and the common control signal; the driver circuit may also have a parasitic coupling between its driver input and the current node and the control circuit may isolate the parasitic coupling between the current node and the driver input.

US Patent:

6583740, Jun 24, 2003

Filed:

Nov 21, 2001

Appl. No.:

09/990983

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341120, 341136, 327416, 323312

Abstract:

A calibrated current source includes current source having an output node; a calibration circuit; a load circuit; a cascode switching circuit including a pair of cascode switches, one connected between the local circuit and output node, the other connected between the calibration circuit and the output node; and a bias circuit selectively applying a bias voltage to the cascode switches to selectively connect the load circuit and the calibration circuit to the output node while maintaining a constant voltage at the output node and across the current source to provide a consistent current to the load and calibration circuits.

US Patent:

6674309, Jan 6, 2004

Filed:

Nov 12, 2002

Appl. No.:

10/292114

Inventors:

Douglas A. Mercer - Bradford MA
Michael P. Timko - Andover MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G01R 2500

US Classification:

327 9, 327 94

Abstract:

A method and apparatus for measuring and controlling the phase difference or time difference between two signals is presented. In some embodiments two sample and hold (S/H) circuits are arranged as a cooperating system that alternately samples a first signal using the second as a reference. Chopping may be used at the input or output of the S/H circuits. In some embodiments, accurate measurement of digital signal phase differences, such as between two square waves, is obtained without the problems associated with traditional pulse-generation techniques that fail at high frequencies and short pulse lengths.

US Patent:

6738006, May 18, 2004

Filed:

May 6, 2003

Appl. No.:

10/430815

Inventors:

Douglas A. Mercer - Bradford MA
William G. J. Schofield - North Andover MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 341145

Abstract:

A digital to analog converter circuit is segmented into a main digital to analog converting unit including a plurality of current sources and a plurality of cascode units, each current source being connected to a cascode unit and a sub-digital to analog converting unit including a current source connected to a plurality of cascode units. A cascode bias unit is operatively connected to each cascode unit of the main digital to analog converting unit so as to bias each current source of the main digital to analog converting unit to operate at a same drain voltage. A second cascode bias unit is operatively connected to each cascode unit of the sub-digital to analog converting unit so as to bias the current source of the sub-digital to analog converting unit to operate at a same drain voltage. A reference voltage source is operatively connected to an input of the first cascode bias unit and connected to an input of the second cascode bias unit. The tying of the reference voltage source to both cascode bias circuits causes the operating emitter/source to collector/drain voltage of each current source transistor of the main digital to analog converting unit to be equal to the operating emitter/source to collector/drain voltage of the current source transistor of the sub-digital to analog converting unit.

US Patent:

6768438, Jul 27, 2004

Filed:

Jan 24, 2003

Appl. No.:

10/351066

Inventors:

William G. J. Schofield - North Andover MA
Douglas A. Mercer - Bradford MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 166

US Classification:

341144, 327408

Abstract:

Methods and devices for code independent switching in a digital-to-analog converter (DAC) are described. A synchronous digital circuit is triggered by a clocking signal and develops a digital data signal. A current steering circuit has a common source node for supplying current, and develops an analog output signal representative of the digital data signal. Any switching disturbances at the common source node are substantially data independent.

US Patent:

7023255, Apr 4, 2006

Filed:

Jun 23, 2004

Appl. No.:

10/874513

Inventors:

Douglas A. Mercer - Bradford MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03K 3/356

US Classification:

327199, 327201, 327211, 327212, 327218

Abstract:

A digital latch includes a latch circuit having first and second data inputs, first and second data outputs, and a clock signal input. The latch circuit has a first load value relative to a clock driver when data at the first and second data inputs is non-changing. The latch circuit has a second load value relative to a clock driver when data at the first and second data inputs is changing. The digital latch further includes a load compensation circuit operatively connected to the first and second data inputs of the latch circuit and to the first and second data outputs of the latch circuit. The load compensation circuit provides a first compensation load value upon the clock driver when data at the first and second data inputs is non-changing and provides a second compensation load value relative upon the clock driver when data at the first and second data inputs is changing such that a sum of the first load value and the first compensation load value equals a sum of the second load value and the second compensation load value.