Douglas F Ridley

US Patent:

51717166, Dec 15, 1992

Filed:

Jun 3, 1991

Appl. No.:

7/709242

Inventors:

Myron R. Cagan - San Jose CA
Douglas F. Ridley - San Jose CA
Daniel J. Belton - San Jose CA

Assignee:

North American Philips Corp. - New York NY

International Classification:

H01L 2156
H01L 2160

US Classification:

437211

Abstract:

A semiconductor device contains a stress-relief layer (46) having a glass transition temperature below 150. degree. C. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer is preferably made by lithographic patterning.

US Patent:

50459180, Sep 3, 1991

Filed:

Apr 4, 1990

Appl. No.:

7/504710

Inventors:

Myron R. Cagan - San Jose CA
Douglas F. Ridley - San Jose CA
Daniel J. Belton - San Jose CA

Assignee:

North American Philips Corp. - New York NY

International Classification:

H01L 2328
H01L 2934

US Classification:

357 72

Abstract:

A semiconductor device contains a stress-relief layer (46) having a glass transition temperature of 25. degree. C. or less. The layer generally lies above an electrical interconnection system (12) in the device but does not overlie bond pad areas. This substantially alleviates thermally induced stress that could otherwise damage electronic components in the device while simultaneously allowing the maximum stress on electrical conductors (32 and 34) that protrude from the external package coating (48) to occur at bonding areas which can tolerate the stress. The layer preferably is a silicone polymer consisting of exposed photosensitive material.

US Patent:

45691215, Feb 11, 1986

Filed:

Mar 7, 1983

Appl. No.:

6/472804

Inventors:

Sheldon C. P. Lim - Sunnyvale CA
Douglas F. Ridley - Saratoga CA
Saiyed A. Raza - Santa Clara CA
George W. Conner - Ben Lomond CA

Assignee:

Signetics Corporation - Sunnyvale CA

International Classification:

H01L 2120
H01L 21479

US Classification:

29574

Abstract:

In fabricating a PROM cell, an electrical isolation mechanism (44 and 32) is formed in a semiconductive body to separate islands of an upper zone (36) of first type conductivity (N) in the body. A semiconductor impurity is introduced into one of the islands to produce a region (48) of opposite type conductivity (P) that forms a PN junction laterally bounded by the island's side boundaries. A highly resistive amorphous semiconductive layer (58) which is irreversibly switchable to a low resistive state is deposited above the region in such a manner as to be electrically coupled to the region. A path of first type conductivity extending from the PN junction through another of the islands to its upper surface is created in the body to complete the basic cell.