Douglas A Rogers

US Patent:

6504537, Jan 7, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/655103

Inventors:

Henry P. Moreton - Woodside CA
Douglas H. Rogers - Sunnyvale CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1530

US Classification:

345423

Abstract:

A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

US Patent:

6597356, Jul 22, 2003

Filed:

Nov 21, 2000

Appl. No.:

09/718890

Inventors:

Henry P. Moreton - Woodside CA
Justin Legakis - Davis CA
Douglas H. Rogers - Sunnyvale CA

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06T 1720

US Classification:

345423, 345421, 345426, 345427

Abstract:

An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

US Patent:

6600488, Jul 29, 2003

Filed:

Nov 4, 2002

Appl. No.:

10/287988

Inventors:

Henry P. Moreton - Woodside CA
Douglas H. Rogers - Sunnyvale CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1530

US Classification:

345423

Abstract:

A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

US Patent:

6788312, Sep 7, 2004

Filed:

Aug 6, 2001

Appl. No.:

09/922759

Inventors:

Hassane S. Azar - Santa Clara CA
Duncan Andrew Riach - Mountain View CA
Henry P. Moreton - Woodside CA
Douglas H. Rogers - Sunnyvale CA

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G09G 502

US Classification:

345694, 345506

Abstract:

A system, method and computer program product are provided for improving image quality in a graphics pipeline. Initially, a difference is detected between a first pixel of a first frame to be outputted and a corresponding second pixel of a second frame outputted before the first frame. Such difference may be representative of motion which is capable of reducing image quality. A pixel output is then modified if such a difference is detected. This is accomplished utilizing texturing hardware in the graphics pipeline. Thereafter, the pixel output is outputted via a progressive or interlaced display system.

US Patent:

6906716, Jun 14, 2005

Filed:

Apr 17, 2003

Appl. No.:

10/418364

Inventors:

Henry P. Moreton - Woodside CA, US
Justin Legakis - Davis CA, US
Douglas H. Rogers - Sunnyvale CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T017/20

US Classification:

345423, 345421, 345426, 345427, 345505, 345506, 345519

Abstract:

An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

US Patent:

8373717, Feb 12, 2013

Filed:

Apr 25, 2007

Appl. No.:

11/740000

Inventors:

Henry Packard Moreton - Woodside CA, US
Douglas H. Rogers - Gilroy CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G09G 5/00

US Classification:

345582

Abstract:

The symmetrical properties of a group of vertices are leveraged to reconstruct the group using vertex data for a subset of the vertices and a set of control data. The subset of vertices is symmetrical to one or more other subsets of vertices in the group, and the control data includes information to reconstruct the one or more other subsets using the vertex data for the first set of vertices and symmetrical characteristics of the group. In some embodiments, reconstruction is performed using a geometry shader in a graphics processor to compute the additional vertices.

US Patent:

20080266286, Oct 30, 2008

Filed:

Apr 25, 2007

Appl. No.:

11/740009

Inventors:

William Orville Ramey - Santa Clara CA, US
Henry Packard Moreton - Woodside CA, US
Douglas H. Rogers - Gilroy CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345419

Abstract:

A geometry shader of a graphics processor is configured to generate at least a portion of a particle system. The geometry shader receives vertex data including a reference set of vertices. The geometry shader also receives control data including information on how to create additional vertices for the particle system using the vertex data. The geometry shader processes the vertex data and control data to generate the additional vertices for the particle system. In some embodiments, the control data also includes information on other attributes of the generated vertices.

US Patent:

20080266287, Oct 30, 2008

Filed:

Apr 25, 2007

Appl. No.:

11/740016

Inventors:

William Orville Ramey - Santa Clara CA, US
Henry Packard Moreton - Woodside CA, US
Douglas H. Rogers - Gilroy CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345419

Abstract:

A geometry shader of a graphics processor decompresses a set of vertex data representing a simplified model to create a more detailed representation. The geometry shader receives vertex data including a number of vertices representative of a simplified model. The geometry shader decompresses the vertex data by computing additional vertices to create the more detailed representation. In some embodiments, the geometry shader also receives rules data including information on how the vertex data is to be decompressed.