Douglas W Sanders

US Patent:

7698477, Apr 13, 2010

Filed:

Nov 30, 2005

Appl. No.:

11/290096

Inventors:

Jeffrey William Breti - Nashua NH, US
Douglas Elliott Sanders - Framingham MA, US
Harish Bharadwaj - Redwood City CA, US
Suparna Behera - Cupertino CA, US
Gordon Douglas Boyd - Arlington MA, US
Richard John Bombard - Marlborough MA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 19/00
G06F 3/00

US Classification:

710 29, 710 33

Abstract:

A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver. The CCE is operated to selectively process the credit count information stored in the repository, in order to generate an update credit count.

US Patent:

50069802, Apr 9, 1991

Filed:

Jul 20, 1988

Appl. No.:

7/222008

Inventors:

Douglas E. Sanders - Framingham MA
George M. Uhler - Marlborough MA
John F. Brown - Northborough MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 938

US Classification:

364200

Abstract:

A pipelined CPU employs separate microinstruction pipelines for the execution unit and memory management unit. Deadlocks can occur in a pipelined CPU when there is data dependency in two consecutive instructions. The later instruction may stall the pipeline if operands fetched by an earlier instruction are needed, but the earlier instruction is not producing the memory request for the operands because the pipeline is stalled; this results in a deadlock. Using separate micro-pipelines, the earlier instruction is advanced independently of the rest of the pipeline, in the case of a deadlock, so that the operands for the later instruction are provided and the deadlock is broken.

US Patent:

55576222, Sep 17, 1996

Filed:

Jan 4, 1993

Appl. No.:

8/000518

Inventors:

Douglas E. Sanders - Framingham MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1110
H03M 1300

US Classification:

371 491

Abstract:

A parity generator for multibit binary data in which only a subset of bits change at one time includes a circuit for determining whether the number of bits in the subset to be changed is odd or even. A toggle signal generator generates a toggle signal only if the number of bits to be changed is odd. A toggling circuit selectively changes the level of the parity bit in response to the toggle signal.

US Patent:

51558432, Oct 13, 1992

Filed:

Jun 29, 1990

Appl. No.:

7/547597

Inventors:

Rebecca L. Stamm - Boston MA
R. Iris Bahar - Belmont MA
Michael Callander - Hudson MA
Linda Chao - Chelmsford MA
Derrick R. Meyer - Watertown MA
Douglas Sanders - Framingham MA
Richard L. Sites - Boylston MA
Raymond Strouble - Southbridge MA
Nicholas Wade - Marlborough MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1100

US Classification:

395575

Abstract:

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

US Patent:

51931630, Mar 9, 1993

Filed:

Oct 1, 1990

Appl. No.:

7/591197

Inventors:

Douglas E. Sanders - Framingham MA
Michael A. Callander - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1200
G06F 1300

US Classification:

395425

Abstract:

A method and apparatus for monitoring transactions on a system bus for invalidate requests, including a queue for storing the invalidate requests which is divided into two parts. The first part of the queue is contained within a cache controller to ensure that an invalidate request is immediately available for processing when the cache controller is otherwise idle. The second part of the queue is contained within a system interface to ensure that the system interface can detect and respond to more system transactions before the first invalidate request has been processed and to enable the system interface to be immediately aware if the entire queue is full.

US Patent:

51194830, Jun 2, 1992

Filed:

Jul 20, 1988

Appl. No.:

7/221944

Inventors:

William C. Madden - Lexington MA
Douglas E. Sanders - Framingham MA
G. Michael Uhler - Marlborough MA
William R. Wheeler - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 938
G06F 1100

US Classification:

395375

Abstract:

To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information.

US Patent:

20230034817, Feb 2, 2023

Filed:

Apr 11, 2022

Appl. No.:

17/717858

Inventors:

- Waltham MA, US
Roberto CALCEDO DEL HOYO - Concord MA, US
Douglas N. SANDERS - Hudson NH, US
Lisa M. STANEK - Natick MA, US
Samantha SMITH - Watertown MA, US
Richard LU - Somerville MA, US
Christopher TIPPER - Cambridge MA, US
Robert Steven Johnson - Oundle, GB

Assignee:

AFFINIA THERAPEUTICS INC. - Waltham MA

International Classification:

C12N 15/861
C12N 15/74
A61P 25/28

Abstract:

The disclosure pertains to a recombinant adeno-associated virus (rAAV) comprising an Anc80L65 capsid for delivering a polynucleotide (e.g., a transgene) into the central nervous system (CNS). Further provided includes methods for treating CNS diseases using the rAAV and pharmaceutical compositions comprising the rAAV.