Douglas N Sanders

US Patent:

7698477, Apr 13, 2010

Filed:

Nov 30, 2005

Appl. No.:

11/290096

Inventors:

Jeffrey William Breti - Nashua NH, US
Douglas Elliott Sanders - Framingham MA, US
Harish Bharadwaj - Redwood City CA, US
Suparna Behera - Cupertino CA, US
Gordon Douglas Boyd - Arlington MA, US
Richard John Bombard - Marlborough MA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

G06F 19/00
G06F 3/00

US Classification:

710 29, 710 33

Abstract:

A method and apparatus is provided wherein a central Credit Controller Entity (CCE) is connected to a PCIE fabric environment by means of several buses. Flow Control information sent to the CCE over two of the buses indicates the buffer storage capacity that is available at respective Receiver components in the PCIE fabric. The CCE processes the Flow Control information, to generate updates that are sent by a third bus to Transmitter components corresponding to the Receivers. In one useful embodiment, directed to a method of Flow Control management, the CCE provides a repository adapted to store credit count information that represents the available storage capacity of respective Receivers. The method further comprises routing further credit count information from a given Receiver to the CCE, for storage in the repository, following each of successive events that affect the storage capacity of the given Receiver. The CCE is operated to selectively process the credit count information stored in the repository, in order to generate an update credit count.

US Patent:

8116330, Feb 14, 2012

Filed:

Jun 1, 2009

Appl. No.:

12/475838

Inventors:

James W. Keeley - Hollis NH, US
Douglas E. Sanders - Framingham MA, US
Andrew Hyonil Chong - San Jose CA, US

Assignee:

LSI Corporation - Milpitas CA

International Classification:

H04L 12/56

US Classification:

370401

Abstract:

Apparatus and methods for an enhanced bridge device for coupling multiple non-Fiber Channel storage devices to a Fiber Channel Arbitrated Loop (FC-AL) communication medium. Features and aspects hereof provide for FC-AL enhanced circuits for processing loop port bypass (LPB) and loop port enable (LPE) primitive sequences addressed to any target arbitrated loop physical address (T-ALPA) associated with a storage device coupled with the bridge regardless of the present bypassed/non-bypassed status of other T-ALPAs processed by the bridge device and associated with other storage devices coupled with the bridge device.

US Patent:

8379665, Feb 19, 2013

Filed:

Jun 1, 2009

Appl. No.:

12/475694

Inventors:

James W. Keeley - Hollis NH, US
Douglas E. Sanders - Framingham MA, US
Daniel W. Meyer - Brentwood CA, US
Andrew Hyonil Chong - San Jose CA, US
Ju-Ching Tang - Fremont CA, US

Assignee:

LSI Corporation - San Jose CA

International Classification:

H04J 3/02

US Classification:

370462

Abstract:

Apparatus and methods improved fair access to a Fiber Channel Arbitrated Loop (FC-AL) communication medium through a bridge device. The enhanced bridge device provides for a fair access in a currently open access window for all presently requesting devices coupled through the bridge device to the FC-AL communication medium. Thus all devices on the loop whether coupled directly or through a bridge device can be assured fair access to the loop when there are simultaneous requests during an open access window.

US Patent:

51558432, Oct 13, 1992

Filed:

Jun 29, 1990

Appl. No.:

7/547597

Inventors:

Rebecca L. Stamm - Boston MA
R. Iris Bahar - Belmont MA
Michael Callander - Hudson MA
Linda Chao - Chelmsford MA
Derrick R. Meyer - Watertown MA
Douglas Sanders - Framingham MA
Richard L. Sites - Boylston MA
Raymond Strouble - Southbridge MA
Nicholas Wade - Marlborough MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1100

US Classification:

395575

Abstract:

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. A branch prediction method employs a branch history table which records the taken vs. not-taken history of branch opcodes recently used, and uses an empirical algorithm to predict which way the next occurrence of this branch will go, based upon the history table. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

US Patent:

52261506, Jul 6, 1993

Filed:

Oct 1, 1990

Appl. No.:

7/591196

Inventors:

Michael A. Callander - Hudson MA
Linda Chao - Chelmsford MA
Douglas E. Sanders - Framingham MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 1100

US Classification:

395575

Abstract:

A write-back cache memory system is disclosed which includes a source of a sequence of memory addresses and a tag store coupled to the source of addresses and accessed by an index portion of said addresses, which produces information relating to the addresses. The write-back cache memory system also includes an error detector for detecting an error in the tag store information. Circuitry is included for reporting an error and saving the index which caused the error if an error is detected but no error has been previously detected. Comparing circuitry is included for comparing the index causing the current error to the previously saved address if an error is detected and an error has been previously detected; and if the address is not the same, then reporting a fatal error; otherwise, if the index is the same, then not reporting a fatal error.

US Patent:

51194830, Jun 2, 1992

Filed:

Jul 20, 1988

Appl. No.:

7/221944

Inventors:

William C. Madden - Lexington MA
Douglas E. Sanders - Framingham MA
G. Michael Uhler - Marlborough MA
William R. Wheeler - Hudson MA

Assignee:

Digital Equipment Corporation - Maynard MA

International Classification:

G06F 938
G06F 1100

US Classification:

395375

Abstract:

To reduce the processing time required for correcting a fault, the instruction decorder segment and the first execution segment of a pipelined processor are provided with "state silos" that are operative during normal instruction execution to save a sufficient amount of state information to immediately restart the instruction decoder segment and the first execution segment by reloading the state information having been stored in the state silos. The state silos, for example, include a queue of registers clocked by a common clocking signal that is inhibited during correction of the fault. When the fault is corrected, multiplexers select the state information from the silos to be used by the respective pipeline segments. In a preferred embodiment, the instruction decoder segment decodes variable length macroinstructions into operand specifiers and operations to perform upon the specifiers. The first execution segment receives control information when a new operand specifier or operation is decoded, and otherwise holds the previously received control information.

US Patent:

20230034817, Feb 2, 2023

Filed:

Apr 11, 2022

Appl. No.:

17/717858

Inventors:

- Waltham MA, US
Roberto CALCEDO DEL HOYO - Concord MA, US
Douglas N. SANDERS - Hudson NH, US
Lisa M. STANEK - Natick MA, US
Samantha SMITH - Watertown MA, US
Richard LU - Somerville MA, US
Christopher TIPPER - Cambridge MA, US
Robert Steven Johnson - Oundle, GB

Assignee:

AFFINIA THERAPEUTICS INC. - Waltham MA

International Classification:

C12N 15/861
C12N 15/74
A61P 25/28

Abstract:

The disclosure pertains to a recombinant adeno-associated virus (rAAV) comprising an Anc80L65 capsid for delivering a polynucleotide (e.g., a transgene) into the central nervous system (CNS). Further provided includes methods for treating CNS diseases using the rAAV and pharmaceutical compositions comprising the rAAV.