Douglas E Sprague

US Patent:

8239818, Aug 7, 2012

Filed:

Apr 5, 2011

Appl. No.:

13/080055

Inventors:

Craig M. Monroe - South Burlington VT, US
Michael R. Ouellette - Westford VT, US
Douglas E. Sprague - Ellsworth ME, US
Georgy S. Varghese - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716138, 716100, 716101, 716102, 716103, 716104, 716106, 716107, 716110, 716111, 716136, 714718, 714733, 714734

Abstract:

A system and associated data structure that can be utilized within a chip design platform to define the structure of an MBIST architecture. A system for generating a memory built in self test (MBIST) design file in described, including a tool for processing an organization file (Org File), wherein the Org File includes lines of code that dictate a structure of the MBIST design file and conform to a data structure defined by the tool; wherein said data structure provides an infrastructure to describe: associations between MBIST components at a design level; associations between MBIST components and hierarchical test ports at the design level; and a serial order of daisy chains among MBIST components within the design level.

US Patent:

8538718, Sep 17, 2013

Filed:

Dec 14, 2010

Appl. No.:

12/967885

Inventors:

Gary D. Grise - Colchester VT, US
Vikram Iyengar - Pittsburgh PA, US
Douglas E. Sprague - Jericho VT, US
Mark R. Taylor - Essex Junction VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 19/00

US Classification:

702117

Abstract:

A method of grouping clock domains includes: separating a plurality of test clocks into a plurality of domain groups by adding to each respective one of the plurality of domain groups those test clocks that originate from a same clock source and have a unique clock divider ratio; sorting the domain groups in decreasing order of size; and creating a plurality of parts by adding the respective one of the plurality of domain groups to a first one of the plurality of parts in which already present test clocks have a different clock source, and creating a new part and adding the respective one of the plurality of domain groups to the new part when test clocks present in the respective one of the plurality of domain groups originate from a respective same clock source and have a different clock divider ratio as test clocks present in all previously-created parts.

US Patent:

8595678, Nov 26, 2013

Filed:

Feb 3, 2012

Appl. No.:

13/365370

Inventors:

Craig M. Monroe - South Burlington VT, US
Michael R. Ouellette - Westford VT, US
Douglas E. Sprague - Ellsworth ME, US
Michael A. Ziegerhofer - Jeffersonville VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716136, 716106, 716111, 716116

Abstract:

Disclosed is a program for creating a checking-statement which can be subsequently used to validate interconnections between logic blocks in a circuit design. The checking-statement is created by taking a description of how logic blocks in a circuit design are associated to one another (if at all), and cross referencing the description with rule statements specific to each logic block defining the allowable connections between the specific logic block and other logic blocks.

US Patent:

20140040685, Feb 6, 2014

Filed:

Aug 6, 2012

Appl. No.:

13/567127

Inventors:

Craig M. Monroe - South Burlington VT, US
Michael R. Ouellette - Westford VT, US
Douglas E. Sprague - Jericho VT, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G11C 29/12

US Classification:

714718, 714E11169

Abstract:

Aspects of the invention provide for creating a built-in-self-test (BIST) organizational file for an integrated circuit (IC) chip. In one embodiment, a method includes: receiving a design file including a hierarchy of memory modules, each module including a plurality of memory wrappers; scanning each memory wrapper in each hierarchical level of memory modules for a BIST type; creating, based on the hierarchical level and the BIST type, an ordered list of memory wrappers; adding, based on the BIST type, a BIST engine for each memory wrapper listed in the ordered list; and adding a plurality of references statements to the ordered list to create the BIST organizational file.

US Patent:

6868513, Mar 15, 2005

Filed:

Oct 26, 2000

Appl. No.:

09/697364

Inventors:

Sally S. Botala - Colchester VT, US
Dale B. Grosch - Burlington VT, US
Donald L. LaCroix - Jericho VT, US
Douglas E. Sprague - Jericho VT, US
Randolph P. Steel - Essex Junction VT, US
Anthony K. Stevens - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R031/28
G01R027/28
G01R031/00
G01R031/14
G06F011/00

US Classification:

714738, 702118, 702119, 702123

Abstract:

A method, system and software for automatically generating a test environment for testing a plurality of devices (DUTs) under test in a test system. The multiple devices are tested by mapping the plurality of DUTs into pins of the tester system to create pin data; inputting into a test program generator pattern data, generic test program rules and the pin data; generating a multi-DUT test program and multi-DUT pattern data; and controlling the test system through the test program. The resulting fail data is then logged to each DUT.

US Patent:

20170108549, Apr 20, 2017

Filed:

Oct 19, 2015

Appl. No.:

14/886739

Inventors:

- GRAND CAYMAN, KY
Mark R. TAYLOR - Essex Junction VT, US
Baalaji Konda Ramamoorthy - Bangalore, IN
Douglas E. Sprague - Ellsworth ME, US
Greeshma Jayakumar - Ernakulam, IN

International Classification:

G01R 31/317
G01R 31/3177

Abstract:

a method includes: defining a plurality of clock architecture attributes for a plurality of clock domains to be tested; assigning each one of the plurality of clock domains to a first test group; and refining the assignment of each one of the plurality of clock domains based on the plurality of clock architecture attributes until each of the plurality of clock domains is grouped into a current test group.

US Patent:

20150039950, Feb 5, 2015

Filed:

Jul 31, 2013

Appl. No.:

13/955401

Inventors:

- Armonk NY, US
Michael R. Ouellette - Westford VT, US
Douglas E. Sprague - Ellsworth ME, US
Michael A. Ziegerhofer - Jeffersonville VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 11/27

US Classification:

714718

Abstract:

A method to produce a description file of Joint Test Action Group (JTAG) capture-shift test data registers to be used to interpret a test result of a memory included in an integrated circuit structure that is configured for testing integrated circuit memory. A computer extracts, from a first data file, the names a memory built in self test instance, a memory built in self test port name, and a name of a first memory. The first data file controls the hierarchical and architectural arrangement of components of an integrated circuit. The first data file describes a hierarchical order of an architectural arrangement of the components, electrical pathways, and connections between the components and the electrical pathways of an integrated circuit design. The computer adds the extracted names into the description file such that the description file is configured to interpret a test result of a memory.