Douglas J Yoder

US Patent:

6802555, Oct 12, 2004

Filed:

Aug 12, 2003

Appl. No.:

10/639043

Inventors:

Douglas J. Yoder - Nappanee IN
Jerry L. Babcock - Waukesha WI

Assignee:

Actuant Corporation - Glendale WI

International Classification:

B60P 334

US Classification:

296165, 296 2609, 296 2613

Abstract:

A leveling ramp assembly for a vehicle slide-out room includes a ramp member and a face member, the ends of which are mounted to the vehicle floor by a pair of end members. The ramp provides a declined surface extending from the vehicle floor to a base rail from which a channel flange depends defining an outwardly opening horizontal channel. The face member mounts to the front of the ramp member by inserting its support rail into the channel. The channel flange and support rail have corresponding lengthwise grip regions that mate and improve the connection. The assembly is modular in that any number of shorten ramp or face members can be coupled end to end to span the width of the slide-out room and the face member(s) can be interchanged with other face members having various profiles.

US Patent:

49757598, Dec 4, 1990

Filed:

Mar 6, 1989

Appl. No.:

7/318887

Inventors:

Diane W. Sidner - Noblesville IN
Douglas J. Yoder - Sharpsville IN
David E. Moss - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

H01L 2712

US Classification:

357 49

Abstract:

A moat having a flat bottom and tapered side walls is formed in a monocrystalline silicon body (substrate) and extends from a top surface of the substrate into the substrate. An oxide layer is grown over side walls and a bottom of the moat and then is selectively removed from the bottom of the moat to expose silicon. An epitaxial stalk (a recessed mesa) is grown on the silicon at the bottom of the moat to a height which makes its top at least coplanar with the top surface of the substrate.

US Patent:

50343424, Jul 23, 1991

Filed:

Jun 29, 1990

Appl. No.:

7/546289

Inventors:

Diane W. Sidner - Noblesville IN
Douglas J. Yoder - Sharpsville IN
David E. Moss - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

H01L 21302
H01L 21306

US Classification:

437 67

Abstract:

A moat having a flat bottom and tapered side walls is formed in a monocrystalline silicon body (substrate) and extends from a top surface of the substrate into the substrate. An oxide layer is grown over side walls and a bottom of the moat and then is selectively removed from the bottom of the moat to expose silicon. An epitaxial stalk (a recessed mesa) is grown on the silicon at the bottom of the moat to a height which makes its top at least coplanar with the top surface of the substrate.

US Patent:

48856215, Dec 5, 1989

Filed:

May 2, 1988

Appl. No.:

7/189446

Inventors:

Douglas J. Yoder - Sharpsville IN
Ronald E. Brown - Kokomo IN
Paul E. Stevenson - Kokomo IN
Donald L. Hornback - Kokomo IN
Ronald K. Leisure - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

H01L 2984
H01L 2996

US Classification:

357 26

Abstract:

A monolithic pressure sensitive silicon integrated circuit is formed by first providing a localized etch-stop layer on one surface of the silicon chip, then growing successive epitaxial layers of opposite conductivity types over this surface. In the upper of the two layers, there is formed a bridge of four piezoresistors overlying the periphery of the etch-stop layer and the conditioning circuitry for amplifying the output of the bridge including both lateral and vertical junction transistors. The back surface of the chip is etched anisotropically to form a cavity that leaves a thin diaphragm underlying the bridge of the four piezoresistors.

US Patent:

49771019, Dec 11, 1990

Filed:

Aug 21, 1989

Appl. No.:

7/396250

Inventors:

Douglas J. Yoder - Sharpsville IN
Ronald E. Brown - Kokomo IN
Paul E. Stevenson - Kokomo IN
Donald L. Hornback - Kokomo IN
Ronald K. Leisure - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

H01L 2170
H01L 21265

US Classification:

437 51

Abstract:

A monolithic pressure sensitive silicon integrated circuit is formed by first providing a localized etch-stop layer on one surface of the silicon chip, then growing successive epitaxial layers of opposite conductivity types over this surface. In the upper of the two layers, there is formed a bridge of four piezoresistors overlying the periphery of the etch-stop layer and the conditioning circuitry for amplifying the output of the bridge including both lateral and vertical junction transistors. The back surface of the chip is etched anisotropically to form a cavity that leaves a thin diaphragm underlying the bridge of the four piezoresistors.

US Patent:

49931431, Feb 19, 1991

Filed:

Mar 27, 1990

Appl. No.:

7/488349

Inventors:

Diane W. Sidner - Noblesville IN
Douglas J. Yoder - Sharpsville IN
David E. Moss - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

G01L 708
G01L 906

US Classification:

296211

Abstract:

A pressure sensor uses a monocrystalline silicon chip that has a diaphragm portion in which strain gages are formed that overlie a buried cavity. The cavity is formed by a single sided semiconductor fabrication process that includes a pair of preferential etching steps and an epitaxial deposition step.

US Patent:

49457691, Aug 7, 1990

Filed:

Mar 6, 1989

Appl. No.:

7/319023

Inventors:

Diane W. Sidner - Noblesville IN
Douglas J. Yoder - Sharpsville IN
David E. Moss - Kokomo IN

Assignee:

Delco Electronics Corporation - Kokomo IN

International Classification:

G01L 708
G01L 906

US Classification:

73727

Abstract:

A pressure sensor uses a monocrystalline silicon chip that has a diaphragm portion in which strain gages are formed that overlie a buried cavity. The cavity is formed by a single sided semiconductor fabrication process that includes a pair of preferential etching steps and an epitaxial deposition step.