Duane E Carter

Address:

13501 Sage Grouse Dr, Austin, TX 78729

Phone:

3602492033

VIN:

1D7HW78N08S525558

Make:

DODGE

Model:

DAKOTA

Year:

2008

US Patent:

6423627, Jul 23, 2002

Filed:

Sep 28, 1999

Appl. No.:

09/407560

Inventors:

Duane E. Carter - Plano TX
Ming J. Hwang - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438620, 438233, 438587, 438672

Abstract:

Contacts for an electronic device are formed by providing a substrate ( ) that has at least two access line structures ( ) for a memory array ( ) and a periphery structure ( ) for a peripheral circuit ( ) to the memory array ( ). A first insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), and the periphery structure ( ). A contact area of the periphery structure ( ) is exposed through the first insulative layer ( ) while maintaining the first insulative layer ( ) over at least a contact overlap portion ( ) of the access line structures ( ). A second insulative layer ( ) is formed outwardly of the substrate ( ), the access line structures ( ), the periphery structure ( ), and the first insulative layer ( ). A self-aligned contact hole ( ) overlapping the contact overlap portion ( ) of the access line structures ( ) and a periphery contact hole ( ) overlapping the contact area ( ) of the periphery structure ( ) are formed through the second insulative layer ( ) with a same mask ( ). A self-aligned contact ( ) is formed in the self-aligned contact hole ( ) and a periphery contact ( ) is formed in the periphery contact hole ( ).

US Patent:

6544886, Apr 8, 2003

Filed:

May 18, 2000

Appl. No.:

09/574731

Inventors:

Duane E. Carter - Plano TX
Yung Liu - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 214763

US Classification:

438637, 438635, 438680, 438687, 438688, 438768

Abstract:

A method of isolating an exposed conductive surface. An aluminum layer ( ) is selectively formed over the exposed conductive ( ) surface (e. g. , Cu) but not over the surrounding dielectric ( ) surface using a thermal CVD process. The aluminum layer ( ) is then oxidized to form a thin isolating aluminum-oxide ( ) over only the conductive surface. The isolating aluminum-oxide provides a barrier for the Cu while taking up minimal space and reducing the effective dielectric constant.

US Patent:

6967054, Nov 22, 2005

Filed:

Mar 6, 2003

Appl. No.:

10/382675

Inventors:

Jay Bernard Kirk - Plano TX, US
Zuhair Hilali - Dallas TX, US
Duy Phan - Garland TX, US
Darren S. Lee - Dallas TX, US
Duane E. Carter - Plano TX, US
Gary A. Evans - Plano TX, US
David Alan Willis - Dallas TX, US

Assignee:

Photodigm, Inc. - Richardson TX

International Classification:

B32B003/00
G02F001/00
G03C005/00

US Classification:

428156, 428120, 428167, 428172, 359321, 359566, 430322

Abstract:

A uniform coating is provided using surface features. Multiple ridges or other shapes are fabricated near an area of interest to allow for uniform coating in between the ridges. Areas at either ends of the ridges are left open to allow for excess pooling of photoresist liquid and to aid in obtaining uniform coating. The photoresist liquid or other coating fluid is applied to the sample and spun dry. A soft-bake process is performed to evaporate remaining solvents. An element, such as a diffractive, refractive, or reflective grating structure, is then formed in the area of interest using the uniform photoresist coating.

US Patent:

48747238, Oct 17, 1989

Filed:

Jul 16, 1987

Appl. No.:

7/074375

Inventors:

Rhett B. Jucha - Celeste TX
Duane E. Carter - Plano TX
Cecil J. Davis - Greenville TX
Sue E. Crank - Coppell TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306

US Classification:

437245

Abstract:

A thin film etching process, wherein the rate of deposition of a robust sidewall passivant is controlled so that passivants can be continually deposited on the sidewalls of the resist pattern to change the geometry of the resist pattern during the processing step. That is, the existing pattern is modified as if a sidewall filament has been deposited on it, which can be advantageous for many purposes, without the added process complexity required by a sidewall filament process.

US Patent:

58353364, Nov 10, 1998

Filed:

Feb 24, 1997

Appl. No.:

8/818466

Inventors:

Richard L. Knipe - McKinney TX
Duane E. Carter - Plano TX
Lionel S. White - Dallas TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H02N 1300

US Classification:

361233

Abstract:

A method of operating a micromechanical device. The device is in a first state. Data for the next state of the device is loaded onto the activation circuitry of the device, where the next state may be the same state the device is currently in, or a state different from the first state. The equilibrium of the device is shifted away from the next state, by making the data appear complementary to the true data for the next state. When the trapping field is removed or lowered, and a signal to start the transition is provided, the device moves to its new state and the trapping field is reapplied. The data can be made to look complementary by either loading the complements to the true data, or by reversing the polarity of the trapping field.

US Patent:

62820109, Aug 28, 2001

Filed:

May 6, 1999

Appl. No.:

9/306271

Inventors:

Frank C. Sulzbach - Dallas TX
Brian L. Ray - Richardson TX
G. Sreenivas - Dallas TX
Duane E. Carter - Plano TX
Henry W. Trombley - Bristol VT
Austin L. Huang - Vancouver WA
James D. Huffman - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G02F 103

US Classification:

359249

Abstract:

A spatial light modulator with an anti-reflective coating (ARC) 100 integrated into its structure. The manufacturing of the device is altered to include deposition of an ARC 100, and any necessary patterning and etching to allow the elements of the array to operate properly. The ARC could reside in several places of the element structure including over the addressing circuitry 26, over a middle layer 32 or on the underside of the reflective structure 10. Micromechanical spatial light modulators, as well as non-moving modulators, such as reflective and transmissive LCD modulators can use the invention.

US Patent:

61001880, Aug 8, 2000

Filed:

Jul 1, 1998

Appl. No.:

9/108474

Inventors:

Ming Hwang - Dallas TX
Dick N. Anderson - Plano TX
Duane E. Carter - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 2144

US Classification:

438653

Abstract:

A metal-poly stack gate structure and associated method for forming a conductive barrier layer between W and poly in the metal-gate stack gate structure. The process includes the steps of depositing doped silicon on a substrate; forming nitride on the deposited silicon; depositing a metal on the nitride to form a metal/nitride/deposited silicon stack; and thermally treating the stack to transform the nitride into a conductive barrier layer between the metal and the deposited silicon. The thermal treatment transforms the nitride layer (SiN. sub. x or SiN. sub. x O. sub. y) into a conductive barrier (WSi. sub. x N. sub. y or WSi. sub. x N. sub. y O. sub. z) to form a W/barrier/poly stack gate structure. The barrier layer blocks reaction between W and Si, enhances sheet resistance, enhances adhesion between the W and the poly, and is stable at high temperatures.

US Patent:

52525066, Oct 12, 1993

Filed:

May 5, 1992

Appl. No.:

7/879697

Inventors:

Duane E. Carter - Plano TX
William R. McKee - Plano TX
Gishi Chung - Dallas TX
Fred D. Fishburn - Richardson TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H01L 21306

US Classification:

437 47

Abstract:

A method is disclosed for preventing formation of undesirable polysilicon word line gate filaments in integrated circuit devices such as VLSI dynamic random access memories employing field plate isolation. Before the word lines are processed, an oxide layer is formed in the field plate openings beneath sidewalls of nitride along the edges of the field plate openings. The oxide layer partially fills an undercut area beneath a dip out of the sidewall of nitride. The dip out of the sidewall of nitride is removed. The removal of the dip out and the partial filling of the undercut area reduces the possibility of polysilicon word line filaments from forming around the edge of the field plate openings in the undercut area when the word lines are later added. A field plate isolated memory device is also disclosed wherein along the edges of the field plate openings, the partially filling oxide layer and the sidewall nitride layer are approximately coincident.