Duy K Truong

US Patent:

6441658, Aug 27, 2002

Filed:

Aug 14, 2001

Appl. No.:

09/930749

Inventors:

Brian Richard Taraci - Foothill Ranch CA
Duy Duc Truong - Fontana CA

Assignee:

RGB Systems, Inc. - Anaheim CA

International Classification:

H03L 706

US Classification:

327147, 348194

Abstract:

This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the users display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the Phase Locked Loop based on user selected output resolution.

US Patent:

63169746, Nov 13, 2001

Filed:

Aug 26, 2000

Appl. No.:

9/648793

Inventors:

Brian Richard Taraci - Foothill Ranch CA
Duy Duc Truong - Fontana CA

Assignee:

RGB Systems, Inc. - Anaheim CA

International Classification:

H03L 706

US Classification:

327147

Abstract:

This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user's display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the first Phase Locked Loop based on user selected output resolution.