Dzung N Hoang

age ~67

from San Jose, CA

Also known as:
  • Dzung Ngoc Hoang
  • Dzung Ngoc Te Hoang
  • Dzung T Hoang
  • Dung N Hoang
  • Dzung N Do
  • Thanh Ndo
  • Null Null
Phone and address:
5213 Mill Creek Ln, San Jose, CA 95136
4083631503

Dzung Hoang Phones & Addresses

  • 5213 Mill Creek Ln, San Jose, CA 95136 • 4083631503
  • 1074 Kitchener Cir, San Jose, CA 95121 • 4082698213

Resumes

Dzung Hoang Photo 1

Video Codec Algorithms Engineer

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Location:
10266 Beardon Dr, Cupertino, CA 95014
Industry:
Consumer Electronics
Work:
Zenverge since Feb 2006
Chief Video Scientist
Education:
Brown University 1990 - 1997
Doctorates, Doctor of Philosophy, Computer Science
Duke University 1994 - 1996
Tulane University 1986 - 1990
Bachelors, Bachelor of Science, Electrical Engineering, Computer Science
Louisiana School For Math, Science, and the Arts 1984 - 1986
George Mason University
Bachelor of Applied Science, Bachelors
Skills:
Algorithms
Signal Processing
H.264
Video Compression
Soc
Digital Signal Processors
Video Processing
Embedded Systems
Firmware
C
Video
Fpga
C++
Mpeg 4
Device Drivers
Video Coding
Embedded Software
Arm
Software Engineering
Mpeg
Debugging
Asic Modeling
Digital Signal Processing
Mpeg2
Programming
Digital Tv
Image Processing
Streaming Media
System on A Chip
Cluster Computing
Embedded Linux
Rtos
Hevc
Video Codec
Research
Patent Preparation
Audio Visual System Design
Communication
Personal Finance
Languages:
English
Vietnamese
Certifications:
Negotiating Your Job Offer
Dzung Hoang Photo 2

Dzung Hoang

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Us Patents

  • Motion-Adaptive De-Interlacing Method And System For Digital Televisions

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  • US Patent:
    6847405, Jan 25, 2005
  • Filed:
    Sep 14, 2001
  • Appl. No.:
    09/953465
  • Inventors:
    Chi-Yuan Hsu - San Jose CA, US
    Dzung Tien Hoang - San Jose CA, US
  • Assignee:
    Sony Corporation - Tokyo
    Sony Electronics, Inc. - Park Ridge NJ
  • International Classification:
    H04N 1100
  • US Classification:
    348452, 348700
  • Abstract:
    One embodiment of the present invention provides a method and system for transforming a video bitstream in an interlaced format into a progressive format which can be displayed by a digital television. For example, the present embodiment utilizes the pixel information of a current field, previous field, and future field of the interlaced video bitstream to try to determine what the original content is of the missing lines of the current field. Specifically, the present embodiment utilizes different sets of pixel information in order to estimate the amount of motion that exist within a video bitstream. In this manner, the present embodiment is able to more closely determine the original value of the missing pixels of each field of the interlaced video bitstream. Therefore, the present embodiment provides a de-interlacing function enabling digital televisions to receive interlaced video bitstreams and display them in the progressive format.
  • Hypothetical Reference Decoder For Compressed Image And Video

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  • US Patent:
    7257162, Aug 14, 2007
  • Filed:
    Jun 19, 2003
  • Appl. No.:
    10/600163
  • Inventors:
    Eric Viscito - San Francisco CA, US
    Dzung T. Hoang - San Jose CA, US
  • Assignee:
    Conexant Systems, Inc. - Newport Beach CA
  • International Classification:
    H04N 7/12
  • US Classification:
    37524025, 375240, 37524001, 37524012
  • Abstract:
    One method for analyzing a bitstream having a plurality of compressed pictures comprises computing an initial arrival time and a final arrival time of a compressed picture, wherein the initial arrival time is equal to an earlier of the final arrival time of the immediately previous compressed picture or equal to a sum of a fixed time plus a sum of removal delays of all of the compressed pictures between the first compressed picture following the buffering period message and the compressed picture, including the compressed picture, and wherein the final arrival time is equal a sum of the initial arrival time and a time calculated based on the number of bits associated with the compressed picture at the bit rate; and verifying that a difference between the final removal time and the initial arrival time does not exceed the time for reaching the buffer size at the bit rate.
  • Hypothetical Reference Decoder With Low Start-Up Delays For Compressed Image And Video

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  • US Patent:
    7532670, May 12, 2009
  • Filed:
    Sep 5, 2003
  • Appl. No.:
    10/655698
  • Inventors:
    Eric Viscito - San Francisco CA, US
    Dzung T. Hoang - San Jose CA, US
  • Assignee:
    Conexant Systems, Inc. - Newport Beach CA
  • International Classification:
    H04N 7/12
  • US Classification:
    37524025, 375240, 37524001, 37524012
  • Abstract:
    In one aspect, a method for encoding pictures is provided. The method is applied to each picture in a sequence of pictures, and the method comprises the steps of assigning a pre-decoder buffer removal time to the picture; selecting, for the picture, a number of bits, wherein the time-equivalent of the number of bits is no greater than a difference based on the pre-decoder buffer removal time of the picture and an initial arrival time of the picture into a pre-decoder buffer; and compressing the picture to generate the number of bits. The method may further include the step of allocating a first number of bits for compressing the picture and one or more number of bits for compressing one or more future pictures, wherein the future pictures are in the pre-decoder buffer at the pre-decoder buffer removal time of the current picture.
  • Perceptually Adaptive Quantization Parameter Selection

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  • US Patent:
    8064517, Nov 22, 2011
  • Filed:
    Sep 7, 2007
  • Appl. No.:
    11/852199
  • Inventors:
    Eric Viscito - Saratoga CA, US
    Dzung Hoang - Austin TX, US
  • Assignee:
    Zenverge, Inc. - Cupertino CA
  • International Classification:
    H04N 11/02
    G06K 9/46
    H04N 7/12
  • US Classification:
    37524003, 382239, 382252
  • Abstract:
    A system (and a method) are disclosed for adaptively selecting quantization parameter for each region of input video signal to be encoded within a video processing system. The system includes a frame partition module, an edge feature detector, a macroblock adaptive quantization energy (AQEnergy) evaluator and a macroblock adaptive quantization parameter selector. The frame partition module partitions a frame of an input video signal into smaller blocks of pixel data. The edge feature detector generates an edge direction histogram for each block to be encoded. The macroblock AQEnergy evaluator receives the edge direction histogram of the block, calculates the AQEnergy of the block and generates the adaptive quantization score (AQScore) of the macroblock. The macroblock adaptive quantization parameter selector selects an appropriate macroblock quantization parameter corresponding to the macroblock AQScore by a combination of programmable scaling and threshold logic.
  • Hypothetical Reference Decoder With Low Start-Up Delays For Compressed Image And Video

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  • US Patent:
    8160153, Apr 17, 2012
  • Filed:
    Mar 31, 2009
  • Appl. No.:
    12/384180
  • Inventors:
    Eric Viscito - San Francisco CA, US
    Dzung T. Hoang - San Jose CA, US
  • Assignee:
    Conexant Systems, Inc. - Newport Beach CA
  • International Classification:
    H04N 7/12
  • US Classification:
    37524025, 37524001, 37524012
  • Abstract:
    In one aspect, a method for encoding pictures is provided. The method is applied to each picture in a sequence of pictures, and the method comprises the steps of assigning a pre-decoder buffer removal time to the picture; selecting, for the picture, a number of bits, wherein the time-equivalent of the number of bits is no greater than a difference based on the pre-decoder buffer removal time of the picture and an initial arrival time of the picture into a pre-decoder buffer; and compressing the picture to generate the number of bits. The method may further include the step of allocating a first number of bits for compressing the picture and one or more number of bits for compressing one or more future pictures, wherein the future pictures are in the pre-decoder buffer at the pre-decoder buffer removal time of the current picture.
  • Intermediate Compression Of Reference Frames For Transcoding

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  • US Patent:
    8199820, Jun 12, 2012
  • Filed:
    Jan 28, 2009
  • Appl. No.:
    12/361440
  • Inventors:
    Anthony D. Masterson - Saratoga CA, US
    Dzung Tien Hoang - Austin TX, US
  • Assignee:
    Zenverge, Inc. - Santa Clara CA
  • International Classification:
    H04N 7/12
    G01R 31/08
  • US Classification:
    37524012, 37524003, 370232
  • Abstract:
    A system (and a method) for compressing reference frames in a video transcoder. A transcoder receives a compressed input stream in a first compressed format and output a compressed output stream in a second compressed format. A decoder and an encoder in the transcoder use compressed reference frames. The reference frames are compressed by transforming a block of pixels from a spatial domain to a frequency domain to generate a coefficient array. The coefficient array is quantized and encoded to compress the size of the coefficients array to the size of a fixed bucket. The values of the entropy coded and quantized array are stored in a memory for use in decoding and/or encoding.
  • Streamlined Transcoder Architecture

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  • US Patent:
    8311114, Nov 13, 2012
  • Filed:
    Dec 6, 2006
  • Appl. No.:
    11/567678
  • Inventors:
    Anthony D. Masterson - Saratoga CA, US
    Dzung T. Hoang - Austin TX, US
    Alexander N. Kipnis - Mountain View CA, US
  • Assignee:
    Zenverge, Inc. - Santa Clara CA
  • International Classification:
    H04N 7/36
  • US Classification:
    37524016, 37524012
  • Abstract:
    Systems and methods for a streamlined transcoder architecture. A transcoder system includes an encoder and a decoder. The encoder compares a decoded frame and a encoder reference frame to produce an output stream. The decoder produces the decoded frame including decoder reference frame and the encoder reference frame. The decoded frame is produced from an input stream, and the encoder reference frame is produced from the output stream of the encoder. In one embodiment, the encoder refines motion vectors, quantization, and macroblock type/mode from the input stream for reuse in the output stream. Furthermore, the decoded frames from the input stream can be modified in various ways including changing picture resolution and performing image enhancement on them before encoding.
  • Motion Compensated Noise Reduction Using Shared Motion Estimation Engine

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  • US Patent:
    8351510, Jan 8, 2013
  • Filed:
    Jan 29, 2009
  • Appl. No.:
    12/362436
  • Inventors:
    Anthony D. Masterson - Saratoga CA, US
    Alexander N. Kipnis - Mountain View CA, US
    Dzung Tien Hoang - Austin TX, US
  • Assignee:
    Zenverge, Inc. - Santa Clara CA
  • International Classification:
    H04N 7/12
    G06K 9/36
  • US Classification:
    37524016, 382236
  • Abstract:
    An apparatus and method for generating predictors performs motion estimation of a target macroblock in a target field against data segments in reference fields. The same motion estimation engine is used to perform various image processing operations to efficiently use resources of the apparatus. Different reference fields are used depending on modes of operation. In a deinterlacing mode, deinterlacing is performed using directional interpolation, recursive motion compensated deinterlacing, and motion adaptive deinterlacing.

Googleplus

Dzung Hoang Photo 3

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Youtube

Dzung - Hoang Ca 13

T nh n ln mnh ni ting nht gan. S ch, s mo, s tc , s th... Ln chy xe x...

  • Duration:
    5m 38s

SD: Dzung/Hong San Diego vs Bo/Trung Minnesota

Tennis event at San Diego October-29-2022.

  • Duration:
    45m 19s

SD: Bo/Trung Minnesota vs Dzung/Hong San Diego

Tennis friendly at San Diego October-29-2022.

  • Duration:
    51m 26s

Dzung - Hoang Ca 13 (Guitar Playthrough)

Nhn dp anh em Psychotramps13 ang trn ng ti huyn Nam Giang chuyn nhng ...

  • Duration:
    5m 2s

Dzung - Hoang Ca 13 (ft. Maximus)

Hoang Ca 13 - Composed by Nguyen Nho Truong Sa & Tran Trung Linh - Arr...

  • Duration:
    5m 11s

Dzung Hoang's 30 birthday

My brother's birthday party.

  • Duration:
    6m 40s

Plaxo

Dzung Hoang Photo 11

Dzung Hoang

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Zenverge

Facebook

Dzung Hoang Photo 12

Dzung Hoang

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Dzung Hoang Photo 13

Dzung Hoang

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Dzung Hoang Photo 14

Dzung Hoang

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Dzung Hoang Photo 15

Dzung Hoang

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Dzung Hoang Photo 16

Dzung Hoang

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