Edward Brent Greene

US Patent:

6480205, Nov 12, 2002

Filed:

Jul 22, 1998

Appl. No.:

09/121317

Inventors:

Edward Colton Greene - Portola Valley CA
Patrick Matthew Hanrahan - Portola Valley CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1500

US Classification:

345631

Abstract:

Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e. g. , in 8 bits). The efficiency of hierarchical z-buffering is obtained through hierarchical evaluation of line and plane equations.

US Patent:

6636215, Oct 21, 2003

Filed:

Mar 9, 2001

Appl. No.:

09/802684

Inventors:

Edward C. Greene - Portola Valley CA

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1500

US Classification:

345422

Abstract:

Roughly described, the invention is employed within a z-buffer-system having a host processor and graphics hardware that performs hierarchical z-buffering. The z-buffer system renders three-dimensional scenes having geometric primitives that are organized in bounding boxes or rooms-with-portals. As an image is being generated, some but not all z-pyramid values are written from the graphics system into memory that can be quickly accessed by the host processor. This enables the host processor to perform visibility tests that cull occluded bounding boxes or portals, thereby accelerating rendering by reducing the number of primitives that need to be sent to graphics hardware and processed.

US Patent:

6646639, Nov 11, 2003

Filed:

Jun 19, 2001

Appl. No.:

09/885665

Inventors:

Edward C. Greene - Portola Valley CA
Douglas A. Voorhies - Menlo Park CA
Paolo Sabella - Pleasanton CA
John M. Danskin - Cranston RI
James M. Van Dyke - Austin TX

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 1500

US Classification:

345422

Abstract:

A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the stored near z-values are compared with far z-values computed for other objects in the region. Such comparison indicates whether an object is visible in the region. Based on the comparison, z-values previously stored for image samples in the region are conditionally read from memory.

US Patent:

6768487, Jul 27, 2004

Filed:

Jul 10, 2002

Appl. No.:

10/193400

Inventors:

Edward Colton Greene - Portola Valley CA
Patrick Matthew Hanrahan - Portola Valley CA

Assignee:

Nvidia Corporation - Santa Clara CA

International Classification:

G06T 1500

US Classification:

345422

Abstract:

Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e. g. , in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.

US Patent:

6894689, May 17, 2005

Filed:

Sep 8, 2003

Appl. No.:

10/658171

Inventors:

Edward C. Greene - Portola Valley CA, US
Douglas A. Voorhies - Menlo Park CA, US
Paolo Sabella - Pleasanton CA, US
John M. Danskin - Cranston RI, US
James M. Van Dyke - Austin TX, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T015/00

US Classification:

345422

Abstract:

A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the stored near z-values are compared with far z-values computed for other objects in the region. Such comparison indicates whether an object is visible in the region. Based on the comparison, z-values previously stored for image samples in the region are conditionally read from memory.

US Patent:

7023437, Apr 4, 2006

Filed:

Aug 27, 2002

Appl. No.:

10/230124

Inventors:

Douglas A. Voorhies - Menlo Park CA, US
Edward C. Greene - Portola Valley CA, US
Emmett M. Kilgariff - San Jose CA, US
Svetoslav Tzvetkov - Sunnyvale CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345420, 345419

Abstract:

A system and method are provided for accelerating graphics processing utilizing multiple-pass rendering. Initially, geometry operations are performed on graphics data, and the graphics data is stored in memory. During a first rendering pass, various operations take place. For example, the graphics data is read from the memory, and the graphics data is rasterized. Moreover, first z-culling operations are performed utilizing the graphics data. Such first z-culling operations maintain a first occlusion image. During a second rendering pass, the graphics data is read from memory. Still yet, the graphics data is rasterized and second z-culling operations are performed utilizing the graphics data and the first occlusion image. Moreover, visibility operations are performed utilizing the graphics data and a second occlusion image. Raster-processor operations are also performed utilizing the graphics data, during the second rendering pass.

US Patent:

7375727, May 20, 2008

Filed:

Mar 3, 2005

Appl. No.:

11/073384

Inventors:

Edward Colton Greene - Portola Valley CA, US
Patrick Matthew Hanrahan - Portola Valley CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345422, 345419

Abstract:

Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e. g. , in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.

US Patent:

7952579, May 31, 2011

Filed:

Nov 1, 2007

Appl. No.:

11/933592

Inventors:

Edward Colton Greene - Portola Valley CA, US
Patrick Matthew Hanrahan - Portola Valley CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 15/00

US Classification:

345422, 345419, 345421, 345629

Abstract:

Z-buffer rendering of three-dimensional scenes is made more efficient through a method for occlusion culling by which occluded geometry is removed prior to rasterization. The method uses hierarchical z-buffering to reduce the quantity of image and depth information that needs to be accessed. A separate culling stage in the graphics pipeline culls occluded geometry and passes visible geometry on to a rendering stage. The culling stage maintains its own z-pyramid in which z-values are stored at low precision (e. g. , in 8 bits). The efficiency of hierarchical z-buffering is improved through hierarchical evaluation of line and plane equations.