Edward Tait Guthrie

US Patent:

20120236187, Sep 20, 2012

Filed:

Mar 16, 2011

Appl. No.:

13/049790

Inventors:

Edward Guthrie - Boston MA, US
Masatoshi Sase - , US
Steven Decker - Sandown NH, US
Katsu Nakamura - Andover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04N 5/335

US Classification:

348273, 348294, 348E05091

Abstract:

Previously available analog domain decimation techniques are limited to simple equally-weighted averaging of photosite outputs. Decimation of a Bayer pattern image by an even-factor, such as by two or six, using simple equally-weighted averaging of photosite outputs in the analog domain results in effective sampling locations that are unevenly spaced apart. Standard interpolation of the unevenly spaced effective sampling locations generates image artifacts that reduce the quality of the reconstructed image in the smaller format because standard interpolation methods assume that the effective sampling locations are evenly spaced. Implementations of systems, methods and apparatus disclosed herein aim to produce substantially evenly spaced effective sampling locations in the analog domain. More specifically, in some implementations, the unequally-weighted-average even-factor decimation methods disclosed herein produce substantially more evenly spaced effective sampling locations as compared to the equally-weighted-average even-factor decimation processes previously used in the analog domain.

US Patent:

20190182445, Jun 13, 2019

Filed:

Sep 11, 2018

Appl. No.:

16/127553

Inventors:

- Hamilton, BM
Edward C. GUTHRIE - Charlestown MA, US
Jonathan Ephraim David HURWITZ - Edinburgh, GB

Assignee:

Analog Devices Global Unlimited Company - Hamilton

International Classification:

H04N 5/369
H03M 1/46
H04N 5/378

Abstract:

Embodiments of the present disclosure provide ADCs particularly suitable for PDAF image sensors, which ADCs may have an increased speed and/or reduced design complexity and power consumption compared to conventional implementations. An example ADC for a PDAF image sensor is configured to implement modified SAR techniques which reduce the number of bit trials required for conversion, and enable increased number of samples in a row-conversion time period of the image sensor. The ADC may implement the modified SAR techniques in combination with CMS in pixel readout signal chain, which may reduce noise without a proportionate increase in ADC sample rate.

US Patent:

20190115931, Apr 18, 2019

Filed:

Nov 15, 2018

Appl. No.:

16/192400

Inventors:

Jonathan Ephraim David Hurwitz - Edinburgh, GB
Edward Chapin Guthrie - Charlestown MA, US
Joseph Leabdro Balais Peje - Manila, PH

International Classification:

H03M 1/46
H03M 1/56
H04N 5/378

Abstract:

An ADC circuit that can resolve the most significant bits (MSBs) using a first circuit during a first stage of a multi-stage conversion and resolve the least significant bits (LSBs) using a second circuit during a second stage of the multi-stage conversion. This can be used, for example, in massively parallel applications where the reference level generation can be shared between thousands of converters.

US Patent:

20180309460, Oct 25, 2018

Filed:

Mar 7, 2018

Appl. No.:

15/914833

Inventors:

Abhishek Bandyopadhyay - Winchester MA, US
Daniel Peter Canniff - Boston MA, US
Mariana Tosheva Markova - Cambridge MA, US
Edward Chapin Guthrie - Charlestown MA, US

International Classification:

H03M 3/00
H03M 1/06
H03M 1/36
H03M 3/02
H03M 3/04

Abstract:

A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.

US Patent:

20180091165, Mar 29, 2018

Filed:

Jul 13, 2017

Appl. No.:

15/649313

Inventors:

- Norwood MA, US
Edward C. Guthrie - Charlestown MA, US
Michael C.W. Coln - Lexington MA, US
Mark D. Maddox - Derry NH, US

International Classification:

H03M 1/08

Abstract:

During operation of a SAR ADC, several of the MSBs can be preloaded with predetermined bit decisions prior to carrying out bit trials. A system and method can be provided for incrementally preloading the predetermined bit decisions such as to maintain voltages present at comparator inputs within a limited range of acceptable input voltages.

US Patent:

20140266847, Sep 18, 2014

Filed:

Sep 17, 2013

Appl. No.:

14/028767

Inventors:

Junhua SHEN - Cambridge MA, US
Ronald A. KAPUSTA - Bedford MA, US
Edward C. GUTHRIE - Charlestown MA, US

Assignee:

ANALOG DEVICES, INC. - Norwood MA

International Classification:

H03M 1/38

US Classification:

341158

Abstract:

Embodiments of the present invention may provide an analog-to-digital converter (ADC) system. The ADC system may include an analog circuit to receive an input signal and a reference voltage, and to convert the input signal into a raw digital output. The analog circuit may include at least one sampling element to sample the input signal during a sampling phase and reused to connect to the reference voltage during a conversion phase, and an ADC output to output the raw digital output. The ADC system may also include a digital processor to receive the raw digital output and for each clock cycle, to digitally correct reference voltage errors in the analog-to-digital conversion.