Edward B Jacobs

US Patent:

6631428, Oct 7, 2003

Filed:

May 1, 2000

Appl. No.:

09/562489

Inventors:

Debendra Das Sharma - Santa Clara CA
Edward M. Jacobs - Mountain View CA
John A. Wickeraad - Granite Bay CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 1300

US Classification:

710 29, 710 7, 710 20, 710 33, 710 36, 710 52, 710 54, 710 55

Abstract:

A mechanism that includes an apparatus and method for ensuring that all transactions within any flow control class completes is herein provided. The mechanism includes a plunge transaction that is inserted in each pending transaction queue and which is transmitted to a particular destination device. All prior transactions in a flow control class are deemed to be complete when the destination device receives the plunge transactions in the flow control class.

US Patent:

6813275, Nov 2, 2004

Filed:

Apr 21, 2000

Appl. No.:

09/556052

Inventors:

Debendra Das Sharma - Santa Clara CA
Donald A. Williamson - Cupertino CA
Edward M. Jacobs - Mountain View CA

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

H04L 1256

US Classification:

370412, 710 52

Abstract:

An apparatus and method for an improved asynchronous communication channel between a transmitter and a receiver having separate clocks. The invention provides a simple implementation that solves both the overflow and the underflow problem using the same mechanism, and reduces complexity by elimination of the control split between the two clock domains. A first embodiment of the invention is a method for preventing packet underflow and packet overflow for packets sent across an asynchronous link between a transmitter and a receiver, including a buffer that can store a number of packets greater than an ideal number of packets. The method includes sending a predetermined number of drop-me warning packets and sending one or more drop-me packets from the transmitter to the receiver, receiving the predetermined number of drop-me warning packets and the one or more drop-me packets in the buffer, compensating for packet overflow when the number of packets is greater than the ideal number of packets in the buffer by skipping at least one drop-me packet, and compensating for packet underflow in the buffer when the number of packets is less than the ideal number of packets by stalling access to the buffer for one or more clock cycles. A second embodiment of the invention is an asynchronous link for packets sent between a transmitter having a first clock and a receiver having a second clock, including a buffer to receive the first clock from the transmitter and receive from the transmitter a number of packets equal to or different to a predetermined ideal number of packets, a write pointer, and a read pointer, and a read pointer control circuit to change the read pointer, wherein the buffer can receive drop-me packets, and the read pointer can skip a drop-me packet in the buffer.

US Patent:

7307635, Dec 11, 2007

Filed:

Feb 2, 2005

Appl. No.:

10/906091

Inventors:

Jimmy Yang - Saratoga CA, US
Bo Ye - Cupertino CA, US
Edward M. Jacobs - Sunnyvale CA, US

Assignee:

NeoMagic Corp. - Santa Clara CA

International Classification:

G09G 5/36
G09G 5/00
G06K 9/32

US Classification:

345560, 345649, 345658, 382296, 382297, 348583

Abstract:

A frame buffer stores X pixels per line and Y lines and is read using a burst of B pixels. The un-rotated image is rotated by 90 degrees for display by writing and reading pixels from a line buffer. The line buffer stores a block of B*Y pixels. The frame buffer is logically divided into X/B blocks that are B pixels wide. Blocks are read from the frame buffer from the bottom line to the top with a burst of B pixels per line. An offset locate pixels to read in the line buffer. The offset is B for the first block, and increases by a factor of B for each block read, but wraps around modulo B*Y−1. Pixels for a next block are written into the line buffer to locations vacated as pixels are read out. The increasing offset re-orders the pixels for the rotated display order.

US Patent:

59078537, May 25, 1999

Filed:

Jan 17, 1997

Appl. No.:

8/783918

Inventors:

Edward M. Jacobs - Mountain View CA
Julie W. Moncton - Cupertino CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711 3

Abstract:

A multiprocessor computer architecture containing processor caches that are kept coherent, and in particular, a duplicate cache tag subsystem and method for maintaining duplicate cache tags, are disclosed. The tag width of duplicate cache tags for a processor cache is tailored to available integrated circuit surface area, or to device pin count, without significantly sacrificing system performance. Such partial duplicate tag width may also be reduced at any time during the integrated circuit design phase, should the available integrated circuit surface area or pin-availability decrease. The method disclosed involves requesting data from memory; reading a partial duplicate cache tag list to determine if there is a partial hit; taking the data from the memory if there is no match between a requested address and the partial duplicate cache tag list; holding the data in memory or a requestor module if there is a match between the requested address and the partial duplicate cache tag list; and interrupting processor operation to confirm that the partial duplicate cache tag corresponds to an actual cache tag. The data are taken from the cache if the partial duplicate cache tag matches the actual cache tag and cache status indicates that the data have been modified. The data are taken from memory if the partial duplicate cache tag does not match the actual cache tag or cache status indicates that the data have not been modified.

US Patent:

59580720, Sep 28, 1999

Filed:

Jan 13, 1997

Appl. No.:

8/782964

Inventors:

Edward M. Jacobs - Mountain View CA
Kent A. Dickey - Sunnyvale CA
Kathleen C. Nix - San Jose CA

Assignee:

Hewlett-Packard Company - Palo Alto CA

International Classification:

G06F 1100
G06F 1216
G06F 1300

US Classification:

714 30

Abstract:

A processor-to-memory interface (PMI) for a multiprocessor computer system and a computer testing method are disclosed. The multi-processor computer system provides a processor-to-memory-bus interface for each microprocessor. Each processor-to-memory-bus interface translates between microprocessor and bus protocols and manages respective level-2 (L2) caches. In addition, each interface includes test-event hardware that, when enabled causes test events to be generated with a predetermined repetition rate. The test events are selected for having a non-zero probability of causing system events that are complex, rare and non-fatal. These include assertions of "busy" and "wait" conditions and corrections of single-bit cache errors. The test-event hardware includes a timing generator that determines when test events are to be generated, an event-flag register that determines which events are to be generated, and a test-event generator that generates test-events at the times determined by the timing generator. The timing generator can include a down counter and a register for holding a value to be entered into the counter upon initialization and reset.