Edward J Mcdonald

US Patent:

6560682, May 6, 2003

Filed:

Oct 3, 1997

Appl. No.:

08/943676

Inventors:

Robert J. Miller - Columbia SC
Edward A. McDonald - Baton Rouge LA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711152, 711118, 711151

Abstract:

There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

US Patent:

6754787, Jun 22, 2004

Filed:

Nov 22, 2002

Appl. No.:

10/302372

Inventors:

Robert J. Miller - Columbia SC
Edward A. McDonald - Baton Rouge LA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711152, 711118, 711151

Abstract:

There is provided, for use in a processing system containing a plurality of processors coupled to a main memory, a control circuit for perturbing a lock-step sequence of memory requests received from the processors. The control circuit comprises a memory request generator for generating at least one memory request operable to terminate the lock-step sequence of memory requests.

US Patent:

60264721, Feb 15, 2000

Filed:

Jun 24, 1997

Appl. No.:

8/881413

Inventors:

Larry C. James - West Columbia SC
Arthur F. Cochcroft - West Columbia SC
Peter Washington - Little Mountain SC
Edward A. McDonald - Baton Rouge LA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711147

Abstract:

A hardware method to concurrently obtain memory access locality information for a large number of contiguous sections of system memory (pages) for the purposes of optimizing memory and process assignments in a multiple-node NUMA architecture computer system including a distributed system memory. Page access monitoring logic is included within each processing node which contains a portion of shared system memory. This page access monitoring logic maintains a plurality of page access counters, each page access counter corresponding to a different memory page address within the shared system memory. Whenever the processing node generates a transaction requiring access to a memory address within system memory, the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought. Thus, a record of memory access patterns is created which can be used to optimize memory and process assignments in the computer system.

US Patent:

6128677, Oct 3, 2000

Filed:

Oct 15, 1997

Appl. No.:

8/943677

Inventors:

Robert J. Miller - Columbia SC
Edward A. McDonald - Baton Rouge LA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1336

US Classification:

710 40

Abstract:

A controller is provided, for use in a processing system containing a plurality of processors operable to communicate with a plurality of I/O devices, for directing a first I/O request issued by a first selected one of the plurality of processors to a targeted one of the I/O devices. The controller device comprises a counter for counting a number of retries associated with the first I/O request and comparison circuitry for comparing a count value in the counter with a first predetermined limit, wherein the controller, in response to a determination that the count value in the counter exceeds the first predetermined limit, blocks all other I/O requests issued by the plurality of processors from being directed to the targeted I/O device.

US Patent:

57651957, Jun 9, 1998

Filed:

Dec 8, 1995

Appl. No.:

8/569542

Inventors:

Edward A. McDonald - Baton Rouge LA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 930

US Classification:

711141

Abstract:

A mechanism for distributing interrupts to processors within a multi-processing system including a cache memory corresponding to each processor, a main memory, a bus structure connecting the processors and their associated cache memories with the main memory, and a cache coherency mechanism to maintain data consistency between the cache memories and the main memory. An address within the main memory is assigned to each processor within the system, the assigned address being associated with an interrupt for the processor to which it is assigned. For each processor, a copy of the contents of its assigned address is thereafter read into its corresponding cache memory. Thereafter when a cache coherency operation to update the contents or status of the cache memory address occurs, a comparison is made between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address. An interrupt signal for the processor is generated when the comparison determines a match between the cache memory address presented to the cache memory through the system bus structure and a stored interrupt base address.

US Patent:

60584750, May 2, 2000

Filed:

Sep 22, 1997

Appl. No.:

8/935910

Inventors:

Edward A. McDonald - Baton Rouge LA
Bobby W. Batchler - Columbia SC

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 15177
G06F 1100

US Classification:

713 2

Abstract:

A system for booting a multi-processor computer. If a normal boot attempt fails, different processors are selected, one-at-a-time, for performing the boot routine. During the boot routing, all other processors are held inactive. After boot, processors are tested for health. Non-healthy processors are held inactive, and healthy processors are activated as usual.

US Patent:

60732164, Jun 6, 2000

Filed:

Nov 25, 1997

Appl. No.:

8/980882

Inventors:

Edward A. McDonald - Baton Rouge LA
James M. Ottinger - Duluth GA
Harry W. Scrivener - Columbia SC

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711141

Abstract:

There is disclosed a memory control circuit for use in a processing system containing a plurality of processors coupled to a main memory by a common bus. The memory control circuit is adapted for implementing directory-based coherency in the processing system according to a selected coherency algorithm and comprises: 1) monitoring circuitry for detecting coherency corruption in a coherency directory associated with the main memory; and 2) coherency control circuitry responsive to a detection of coherency corruption in the coherency directory for dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner. In some embodiments, the monitoring circuitry further detects possible system coherency failure conditions external to the coherency directory and the coherency control circuitry responds to the detection of a possible system coherency failure condition by dynamically modifying the selected coherency algorithm, thereby enabling the processing system to shut down in a controlled manner.

US Patent:

57014221, Dec 23, 1997

Filed:

Dec 13, 1995

Appl. No.:

8/573217

Inventors:

James B. Kirkland - West Columbia SC
Edward A. McDonald - Baton Rouge LA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300
G06F 1338

US Classification:

395309

Abstract:

A mechanism for ensuring coherency between a system memory and a cache memory within a processing system including a first split transaction bus, the system memory being connected to the first split transaction bus; a second split transaction bus; a bus agent including the cache memory connected to the second split transaction bus, and a bus interface unit connecting the first and second split transaction busses for transferring bus cycles between the first and second split-transaction busses. The mechanism records bus cycles, such as read cycles, write cycles and cache line invalidate cycles, directed from the first split transaction bus to the second split transaction bus into a transaction queue within the bus interface unit, and sequentially transfers these cycles to the second split transaction bus in the order in which these cycles are recorded into the queue. In another embodiment of the invention, implemented in a system which utilizes a write post negation procedure for to indicate write completion, only read and invalidate cycles received from the first split transaction bus are placed within an ordering queue, while write cycles received from the first split transaction bus are immediately passed through to the second split transaction bus. However, when an invalidate cycle has been recorded to the queue, all write cycles received from the first split transaction bus are held until the queued invalidate cycle has started on the second split transaction bus.