Edward R Sprague

US Patent:

20180024188, Jan 25, 2018

Filed:

Jul 16, 2017

Appl. No.:

15/650970

Inventors:

- Irvine CA, US
GILBERTO OSEGUERA - CORONA CA, US
KARTHIK RANGANATHAN - FOOTHILL RANCH CA, US
EDWARD SPRAGUE - LAKE FOREST CA, US

International Classification:

G01R 31/28

Abstract:

A high volume system level testing of devices with POP structures such as POP memories includes a POP array that includes floating nests that can adjust in the XY direction in order to align individually with respective pads found on the DUTs. The floating nests also include a mechanically fixed PCB that is fixed to the nest and can either mate to a memory contactor array that can accept an unattached POP device such as a memory or can include an attached memory in order to accommodate different POP requirements. In a method, the POP array includes a number of floating nests with memory loaded are aligned and presented to their respective DUTs just prior to testing the combined DUT and POP memory assemblies.