Edward P Yu

US Patent:

6401194, Jun 4, 2002

Filed:

Jan 28, 1997

Appl. No.:

08/790142

Inventors:

Le Trong Nguyen - Monte Sereno CA
Heonchul Park - Cupertino CA
Roney S. Wong - Sunnyvale CA
Ted Nguyen - Saratoga CA
Edward H. Yu - Newark CA

Assignee:

Samsung Electronics Co., Ltd. - Seoul

International Classification:

G06F 9302

US Classification:

712210, 712212, 712 7, 712 8, 712 9, 712 4, 708507, 708524, 708682, 708550, 710 65, 710 66, 710127, 710 50

Abstract:

A vector processor provides a data path divided into smaller slices of data, with each slice processed in parallel with the other slices. Furthermore, an execution unit provides smaller arithmetic and functional units chained together to execute more complex microprocessor instructions requiring multiple cycles by sharing single-cycle operations, thereby reducing both costs and size of the microprocessor. One embodiment handles 288-bit data widths using 36-bit data path slices. Another embodiment executes integer multiply and multiply-and-accumulate and floating point add/subtract and multiply operations using single-cycle arithmetic logic units. Other embodiments support 8-bit, 9-bit, 16-bit, and 32-bit integer data types and 32-bit floating data types.

US Patent:

20080273643, Nov 6, 2008

Filed:

May 4, 2007

Appl. No.:

11/744828

Inventors:

LIN YANG - FREMONT CA, US
HAIYUN YANG - FREMONT CA, US
EDWARD YU - FREMONT CA, US
JIAN WANG - FREMONT CA, US

Assignee:

LEGEND SILICON CORP. - FREMONT CA

International Classification:

H04L 7/00

US Classification:

375368, 375E01037

Abstract:

A transmitter comprising: a digital encoder for encoding incoming digital information; and a digital to analog converter for converting the encoded digital information into analog information is described. The transmitter further comprises an exact time framing block disposed between the digital encoder and the digital to analog converter. The exact time framing block receives the digitally encoded information and comprises a method for synchronization. The method including the steps of: providing a clock signal having at least two adjacent pulses; providing information subjected to transmission in the form of a set of frames; and accommodating a whole number of frames between the two adjacent pulses.

US Patent:

47965363, Jan 10, 1989

Filed:

Jun 23, 1987

Appl. No.:

7/065509

Inventors:

Edward K. Yu - Newark CA
David W. Rogers - Spokane WA

Assignee:

Acurex Corporation - Mountain View CA

International Classification:

F42B 1300

US Classification:

102505

Abstract:

A system for chaff deployment which includes a compartmentalized platelet with the bottom of the compartments formed by preformed releasable tang springs and the top of the compartment by a releasable door. The door is released to open the chamber and the tang springs are thereafter released to eject and deploy the chaff contained in the chamber.

US Patent:

58222316, Oct 13, 1998

Filed:

Oct 31, 1996

Appl. No.:

8/741991

Inventors:

Roney S. Wong - Sunnyvale CA
Edward H. Yu - Newark CA

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

G06F 700

US Classification:

36471508

Abstract:

A modular two level nine bit shift apparatus has a second level shifter which receives nine input data bits and second level shift signals. The second level shifter shifts the nine data bits by 0, 3 or 6 bit positions according to the second level shift signals and outputs nine second level data bits. A first level shifter receives the nine second level data bits and first level shift signals. The first level shifter shifts the nine second level data bits by 0, 1 or 2, bit positions according to the first level shift signals. The first and second level shifter combine to provide a shift of from 0 to 8 bits. The nine bit shifter can also accommodate eight bit data. The 9 bit shift count is decoded by dividing the count into a first block (0, 1, 2), a second block (3, 4, 5) and a third block (6, 7, 8). Block select signals select one of the first, second and third blocks and the bit select signals select one of the three shift counts within each block. A decode of the block select signals are coupled to the second level shifter as the second level shift signal and a decode of the bit select signals are coupled to the first level shifter as the first level shift signal.

US Patent:

58776362, Mar 2, 1999

Filed:

Oct 18, 1996

Appl. No.:

8/733885

Inventors:

Ho D. Truong - San Jose CA
Edward H. Yu - Newark CA
Kathy Ying Chen - Milpitas CA

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

H03K 513
H03K 1700

US Classification:

327 99

Abstract:

An apparatus for multiplexing a pair of test clock signals and a pair of system clock signals onto a pair of output clock signals includes a first means for coupling a first test clock signal to a first output clock signal when a test mode control signal is active, for driving the first output clock signal to an inactive clock signal level when the test mode control signal transitions to an inactive state, and for coupling a first system clock signal to the first output clock signal beginning with a first full clock pulse of the first system clock signal which occurs after the test mode control signal transitions to the inactive state. The apparatus further includes a second means for coupling a second test clock signal to a second output clock when the test mode control signal is active, for driving the second output clock to the inactive clock signal level when the test mode control signal transitions to the inactive state, and for coupling a second system clock signal to the second output clock beginning with a first full clock pulse of the second system clock signal which occurs after the first full clock pulse of the first system clock signal. When exiting the test mode the apparatus ensures that both first and second output clock signals are brought (or held) to an inactive clock signal level, and that system operation begins with the first system clock signal.

US Patent:

58056084, Sep 8, 1998

Filed:

Oct 18, 1996

Appl. No.:

8/733908

Inventors:

Sanghyeon Baeg - Cupertino CA
Edward Yu - Newark CA

Assignee:

Samsung Electronics Co., Ltd.

International Classification:

G01R 3128

US Classification:

371 2231

Abstract:

In an integrated circuit, a clock to simulate the circuit's normal operation is generated from the JTAG clock input TCK.

US Patent:

20170068477, Mar 9, 2017

Filed:

Sep 8, 2016

Appl. No.:

15/259863

Inventors:

- Sunnyvale CA, US
Edward Liang YU - Sunnyvale CA, US

Assignee:

OverNest, Inc. - Sunnyvale CA

International Classification:

G06F 3/06
G06F 21/62
G06F 21/60
G06F 12/14
G06F 17/30

Abstract:

In some embodiments, an apparatus includes a processor configured to receive an instruction to read a data file within a database and an identifier associated with the data file. The processor is also configured to identify, based on the identifier, a set of logical block identifiers associated with a set of storage locations of the database, and retrieve data stored at each storage location from the set of storage locations using the set of logical block identifiers. The processor is then configured to identify, based on the data stored at each storage location from the set of storage locations, a subset of storage locations from the set of storage locations. The data stored at each storage location from the subset of storage locations pertain to the data file. The processor is configured to compile the data file based on the data within the subset of storage locations.