Eileen M Herrin

US Patent:

6762795, Jul 13, 2004

Filed:

Jan 7, 2000

Appl. No.:

09/479703

Inventors:

Leonard P. Chen - Santa Barbara CA
Howard T. Chang - Santa Barbara CA
Eileen M. Herrin - Goleta CA
Mary J. Hewitt - Santa Barbara CA
John L. Vampola - Santa Barbara CA

Assignee:

Raytheon Company - Waltham MA

International Classification:

H04N 314

US Classification:

348295, 348308

Abstract:

A time delay integration circuit in which a number of unit cell inputs ( ) along with their respective switches ( ) are input to a bi-directional BBD circuit ( ). The BBD circuit performs an SCA TDI with reduced ROIC circuitry and compatibility with standard LSI processing. The bi-directional BBD circuit has numerous pairs of MOSFETs ( ) connected in series and numerous storage capacitors ( ) having one of their terminals respectively connected between each of the MOSFET pairs and the other of their terminals alternately connected to clock phases à and Ã. The gates of the MOSFETs in each pair are separated from the clock phases à and à and function respectively as screen gate and transfer clock for one direction of charge flow, and as transfer clock and screen gate for the other direction of charge flow. Transfer direction is changed by switching which MOSFET in a pair becomes clocked as a transfer gate and which becomes a screen gate.