Elizabeth F Stewart

US Patent:

47373075, Apr 12, 1988

Filed:

Jul 23, 1987

Appl. No.:

7/076781

Inventors:

Robert L. Brown - Irving TX
Elizabeth C. Stewart - Houston TX

International Classification:

C11D 348

US Classification:

252106

Abstract:

A cleansing composition capable of removing smegma comprises in an aqueous solution a cleansing agent comprising a mixture of surface active agents in the indicated amounts as follows: (i) from a trace to 0. 2% by weight, based on the total weight of said composition, as an active material of cetylpyridinium chloride, (ii) from a trace to not more than 20 ppm chlorine dioxide, plus 20 ppm sodium hypochlorite, (iii) from a trace to 1% by weight, based on the total weight of said composition as an active material, of polyoxyethylene (20) sorbitan monostearate, and (iv) sodium benzoate from a trace to 2%.

US Patent:

46922628, Sep 8, 1987

Filed:

Sep 18, 1986

Appl. No.:

6/908697

Inventors:

Robert L. Brown - Irving TX
Elizabeth C. Stewart - Houston TX

International Classification:

C11D 348

US Classification:

252106

Abstract:

A cleansing composition capable of removing smegma comprises in an aqueous solution a cleansing agent comprising a mixture of surface active agents in the indicated amounts as follows: (i) from a trace to 0. 2% by weight, based on the total weight of said composition, as an active material of cetylpyridinium chloride, (ii) from a trace to not more than 20 ppm chlorine dioxide, (iii) from a trace to 1% by weight, based on the total weight of said composition as an active material, of polyoxyethylene (20) sorbitan monosterate, and (iv) sodium lauryl sulfate from a trace to 2%.

US Patent:

20220231115, Jul 21, 2022

Filed:

Jan 19, 2021

Appl. No.:

17/152230

Inventors:

- Dallas TX, US
Byron Lovell Williams - Plano TX, US
Elizabeth Costner Stewart - Dallas TX, US
Thomas Dyer Bonifeld - Dallas TX, US

International Classification:

H01L 49/02
H01L 23/552

Abstract:

Described examples include a hybrid circuit having a component. The component has a first conductive element on a substrate having a configuration and having a first periphery and having an extension at the first periphery. The component also has a dielectric on the first conductive element. The component also has a second conductive element having the configuration on the dielectric that is proximate to and aligned with the first conductive element, and has a second periphery, the extension of the first conductive element extending past the second periphery.

US Patent:

20230056046, Feb 23, 2023

Filed:

Feb 28, 2022

Appl. No.:

17/682762

Inventors:

- Dallas TX, US
Elizabeth Costner Stewart - Dallas TX, US
Jeffrey Alan West - Dallas TX, US
Thomas Dyer Bonifield - Dallas TX, US

International Classification:

H01L 23/522
H01L 23/528
H01L 21/768

Abstract:

An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 μm to 6.0 μm, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 μm to 1.0 μm.

US Patent:

20210367044, Nov 25, 2021

Filed:

Aug 10, 2021

Appl. No.:

17/398279

Inventors:

- Dallas TX, US
ELIZABETH COSTNER STEWART - DALLAS TX, US

International Classification:

H01L 29/40
H01L 29/78
H01L 21/308
H01L 29/66
H01L 29/06

Abstract:

An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

US Patent:

20200258987, Aug 13, 2020

Filed:

Feb 8, 2019

Appl. No.:

16/270729

Inventors:

- Dallas TX, US
ELIZABETH COSTNER STEWART - DALLAS TX, US

International Classification:

H01L 29/40
H01L 29/78
H01L 29/06
H01L 29/66
H01L 21/308

Abstract:

An integrated circuit (IC) includes a field-plated transistor including a substrate having a semiconductor surface layer, at least one body region in the semiconductor surface layer, and at least a first trench isolation region adjacent to the body region having at least a first tapered sidewall that has an average angle along its full length of 15 to 70 degrees. A gate is over the body region. A field plate is over the first tapered trench isolation region. A source is on one side of the field plate and a drain is on an opposite side of the field plate. The IC also includes circuitry for realizing at least one circuit function having a plurality of transistors which are configured together with the field-plated transistor that utilize second trench isolation regions for isolation that have an average angle of 75 and 90 degrees.

US Patent:

20200168534, May 28, 2020

Filed:

Nov 28, 2018

Appl. No.:

16/202663

Inventors:

- Dallas TX, US
Sreeram Subramanyam NASUM - Bangalore, IN
Robert H. EKLUND - Plano TX, US
Jeffrey Alan WEST - Dallas TX, US
Byron Lovell WILLIAMS - Plano TX, US
Elizabeth Costner STEWART - Dallas TX, US

International Classification:

H01L 23/495
H01L 21/48
H01L 23/00

Abstract:

In some examples, a multi-chip module (MCM), comprises a first and a second die-attach pad (DAP); a first die comprising a first set of microelectronic devices; a second die comprising a first capacitor and a second capacitor; and a third die comprising a second set of microelectronic devices, where the first and second dies are positioned on the first DAP, and the third die is positioned on the second DAP. The first set of microelectronic devices couples to the first capacitor via a first inter-die connection and the second set of microelectronic devices couples to the second capacitor via a second inter-die connection.

US Patent:

20200058485, Feb 20, 2020

Filed:

Aug 16, 2019

Appl. No.:

16/542628

Inventors:

- Dallas TX, US
Adrian Salinas - Garland TX, US
Elizabeth C. Stewart - Dallas TX, US
Dhanoop Varghese - Plano TX, US
Thomas D. Bonifield - Dallas TX, US

International Classification:

H01L 21/02
H01L 49/02

Abstract:

An integrated circuit a semiconductor substrate includes a device die with includes transistors configured to execute an electrical function. A first interconnect layer of the device die is configured to route electrical signals or power to terminals of the transistors. An interlevel dielectric (ILD) layer is located over the interconnect layer. A metal electrode located over the ILD layer. A dielectric barrier layer is located between the ILD layer and the metal electrode. A scribe seal surrounds the device die. A first opening within the dielectric barrier layer surrounds the metal electrode. Second and third openings within the dielectric barrier layer are located between the first opening and the scribe seal.