Elroy M Lucero

age ~77

from San Jose, CA

Elroy Lucero Phones & Addresses

  • 3295 Oxford Ln, San Jose, CA 95117 • 4082481038
  • Los Angeles, CA
  • Santa Clara, CA
  • 3295 Oxford Ln, San Jose, CA 95117 • 4082192251

Work

  • Company:
    National semiconductor
    Jan 1974 to Sep 2011
  • Position:
    Engineering manager

Education

  • Degree:
    Masters, Master of Science In Electrical Engineering
  • School / High School:
    Santa Clara University
    Jan 1, 1976 to Dec 31, 1978

Skills

Education • Engineering • Electrical Design

Emails

Industries

Semiconductors

Resumes

Elroy Lucero Photo 1

Elroy Lucero

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Location:
San Jose, CA
Industry:
Semiconductors
Work:
National Semiconductor Jan 1974 - Sep 2011
Engineering Manager

Texas Instruments Jan 1974 - Sep 2011
Electrical Design Manager
Education:
Santa Clara University Jan 1, 1976 - Dec 31, 1978
Masters, Master of Science In Electrical Engineering
University of California, Los Angeles 1970 - 1973
Bachelors, Bachelor of Science In Electrical Engineering
Skills:
Education
Engineering
Electrical Design

Us Patents

  • Input Clamp Circuit For 5V Tolerant And Back-Drive Protection Of I/O Receivers Using Cmos Process

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  • US Patent:
    6670840, Dec 30, 2003
  • Filed:
    Jul 26, 2002
  • Appl. No.:
    10/205869
  • Inventors:
    Khusrow Kiani - Oakland CA
    Elroy M. Lucero - San Jose CA
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03K 508
  • US Classification:
    327309, 327312, 361 911, 361111
  • Abstract:
    In a receiver input back-drive protection circuit and method, a pass gate is provided between the high pad voltage and the receiver input and a clamping circuit is provided, to present a reduced voltage to the receiver input during stress mode.
  • Balanced Cells With Fabrication Mismatches That Produce A Unique Number Generator

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  • US Patent:
    7482657, Jan 27, 2009
  • Filed:
    Jun 13, 2003
  • Appl. No.:
    10/461045
  • Inventors:
    Elroy Lucero - San Jose CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H01L 27/01
    H01L 27/12
    H01L 31/0392
    H01L 27/11
    H01L 29/76
  • US Classification:
    257350, 257371, 257393, 257903
  • Abstract:
    A static random access memory (SRAM) is laid out to be balanced so that, when power is applied to the SRAM, the cells of the SRAM have no preferred logic state. In addition, the SRAM is fabricated in a process the emphasizes mismatches so that each individual cell assumes a non-random logic state when power is applied.
  • Dynamic Computation Of Esd Guidelines

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  • US Patent:
    7558720, Jul 7, 2009
  • Filed:
    Jan 9, 2006
  • Appl. No.:
    11/328003
  • Inventors:
    Rajesh R. Berigei - San Jose CA, US
    Elroy Lucero - San Jose CA, US
    Sury Maturi - San Jose CA, US
    Marcel A. ter Beek - Pleasanton CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06F 17/50
  • US Classification:
    703 14, 716 5, 702117, 702118
  • Abstract:
    An automated method for checking electrostatic discharge (ESD) guidelines ensures that a sufficient number of ESD protection cells have been provided in the neighborhood of each pad in an integrated circuit design to ensure adequate current sinking and voltage clamping during the occurrence of an ESD event.
  • Anti-Pirate Circuit For Protection Against Commercial Integrated Circuit Pirates

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  • US Patent:
    7558969, Jul 7, 2009
  • Filed:
    Mar 6, 2003
  • Appl. No.:
    10/383416
  • Inventors:
    Elroy M. Lucero - San Jose CA, US
    Daniel J. Lucero - San Jose CA, US
    Hengyang (James) Lin - San Jose CA, US
    Andrew J. Franklin - San Jose CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G06F 11/07
  • US Classification:
    713193, 713194, 726 17, 726 21, 726 32, 726 33, 710220, 710240, 438 18, 716 1, 716 17
  • Abstract:
    Anti-pirate circuitry is provided for combating the theft of intellectual property contained with semiconductor integrated circuits. The anti-pirate circuit includes a unique number generator that provides a multi-bit die ID data string that is unique to the integrated circuit associated with the anti-pirate circuit. One time programmable (OTP) EPROM circuitry reads the die ID data string at wafer sort and writes the data content to nonvolatile memory. During a subsequent verification cycle, ID comparator circuitry compares the data string provided by the unique number generator to the stored contents of the nonvolatile memory. If the comparison results in a mismatch between more than a predefined number of bits, then the integrated circuit associated with the anti-pirate circuit is not enabled for operation.
  • Method Of Forming A Unique Number

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  • US Patent:
    7602666, Oct 13, 2009
  • Filed:
    Dec 15, 2008
  • Appl. No.:
    12/335163
  • Inventors:
    Elroy Lucero - San Jose CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    G11C 5/14
  • US Classification:
    365226, 365189011
  • Abstract:
    A unique number is formed with logic states from a static random access memory (SRAM), which is laid out to be balanced so that memory cells within the SRAM assume a non-random logic state when power is applied to the SRAM. The unique number is formed by grounding the word lines and bit lines before power is applied to the memory cells, applying power to the memory cells to assume the non-random logic state, reading the non-random logic states held by the memory cells, and forming the unique number from the logic states read from the memory cells.
  • I/O Protection Under Over-Voltage And Back-Drive Conditions By Single Well Charging

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  • US Patent:
    7605619, Oct 20, 2009
  • Filed:
    Mar 21, 2007
  • Appl. No.:
    11/726512
  • Inventors:
    Weiye Lu - Sunnyvale CA, US
    Elroy M. Lucero - San Jose CA, US
    Khusrow Kiani - Oakland CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03K 3/00
  • US Classification:
    327108, 327112
  • Abstract:
    In an I/O driver that includes a cascoded pair of PMOS driver transistors connected to a pair of cascaded NMOS driver transistors and that defines a pad output between the PMOS and NMOS driver transistors, a method of providing the CMOS I/O driver with over-voltage and back-drive protection includes providing circuitry for charging the wells of the PMOS transistors either to VDDIO during normal voltage mode by making use of the power supply, or to a common voltage during over-voltage and back-drive operation using the pad voltage.
  • Load Sense And Active Noise Reduction For I/O Circuit

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  • US Patent:
    7876129, Jan 25, 2011
  • Filed:
    Sep 22, 2008
  • Appl. No.:
    12/234922
  • Inventors:
    Wei Ye Lu - Sunnyvale CA, US
    Elroy Lucero - San Jose CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03K 19/0175
  • US Classification:
    326 82, 326 85, 326 68
  • Abstract:
    An I/O circuit includes load sense and active noise reduction features that result in high speed output signal transitions with very low noise. Capacitive feedback control circuitry controls the point and time at which feedback capacitors are applied to the gate drive of the I/O circuit output stage. Active device feedback control controls the output stage gate drive.
  • Method And System For Reducing I/O Noise And Power

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  • US Patent:
    7928756, Apr 19, 2011
  • Filed:
    Feb 29, 2008
  • Appl. No.:
    12/074176
  • Inventors:
    Weiye Lu - Sunnyvale CA, US
    Elroy M. Lucero - San Jose CA, US
    Thomas Tse - Santa Clara CA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03K 17/16
    H03K 19/003
  • US Classification:
    326 27, 326 86, 326 87, 327109, 327112
  • Abstract:
    In an I/O circuit, noise reduction and power savings are achieved by providing feedback from the output of the I/O driver to control the current through the pre-driver and thereby the current through the driver transistors after a non-zero time delay following a low to high or high to low data signal change.

Youtube

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LUCERO PERFORMING THEIR NEW SONG "DRUNKEN MOON" AT THE MET IN PAWTUCKE...

  • Duration:
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Lucero - 100 Miles on the Other Side of Lones...

Ben NIchols performs "100 Miles on the Other Side of Lonesome", an unr...

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Lucero LIVE @ Salvage Station 5-5-2022

Lucero - Like the great river that flows through Memphis, the music of...

  • Duration:
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Lucero - On the Other Side of Lonesome

Lucero performs "On the Other Side of Lonesome" at WNRN in Charlottesv...

  • Duration:
    3m 8s

Lucero at OpenAir: "The War"

Recorded in the CPR Performance Studio April 19, 2013. Listen to the i...

  • Duration:
    5m 30s

Lucero FULL SET Live @ The Egyptian Room, Ind...

Finally got to see one of my favorite bands Lucero that is on tour wit...

  • Duration:
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