Eric David Finley

Address:

14602 Cardinal Crk Ct, Houston, TX 77062

Phone:

2814887477

VIN:

3FAHP08137R120502

Make:

FORD

Model:

FUSION

Year:

2007

US Patent:

20220188967, Jun 16, 2022

Filed:

Mar 2, 2022

Appl. No.:

17/685117

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets, With such an interchangeable design, cache or DRAM memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20220180468, Jun 9, 2022

Filed:

Feb 17, 2022

Appl. No.:

17/674781

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially and distinctly packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20210256654, Aug 19, 2021

Filed:

Jan 29, 2021

Appl. No.:

17/161941

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20210133913, May 6, 2021

Filed:

Oct 13, 2020

Appl. No.:

17/069188

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20200294180, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355303

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Josh Mastronarde - Sacramento CA, US
Naveen Matam - Rancho Cordova CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the on-board logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

US Patent:

20200294181, Sep 17, 2020

Filed:

Mar 15, 2019

Appl. No.:

16/355377

Inventors:

- Santa Clara CA, US
Lance Cheney - El Dorado Hills CA, US
Eric Finley - Ione CA, US
Varghese George - Folsom CA, US
Sanjeev Jahagirdar - Folsom CA, US
Altug Koker - El Dorado Hills CA, US
Josh Mastronarde - Sacramento CA, US
Iqbal Rajwani - Roseville CA, US
Lakshminarayanan Striramassarma - Folsom CA, US
Melaku Teshome - El Dorado Hills CA, US
Vikranth Vemulapalli - Folsom CA, US
Binoj Xavier - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06T 1/20
G06F 13/40

Abstract:

Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

US Patent:

20190204894, Jul 4, 2019

Filed:

Dec 31, 2017

Appl. No.:

15/859598

Inventors:

- Santa Clara CA, US
Altug Koker - El Dorado Hills CA, US
Yoav Harel - Carmichael CA, US
Kenneth Brand - El Dorado Hills CA, US
Chandra Gurram - Folsom CA, US
Eric Finley - Ione CA, US
Bhushan Borole - Rancho Cordova CA, US
Carlos Nava Rodriguez - Folsom CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/32

Abstract:

Methods and apparatus relating to techniques for resource load balancing based on usage and/or power limits are described. In an embodiment, resource load balancing logic causes a first resource of a processor to operate at a first frequency and a second resource of the processor to operate at a second frequency. Memory stores a plurality of frequency values. The resource load balancing logic also selects the first frequency and the second frequency based on the stored plurality of frequency values. Operation of the first resource at the first frequency and the second resource at the second frequency in turn causes the processor to operate under a power budget. The resource load balancing logic causes change to the first frequency and the second frequency in response to a determination that operation of the processor is different than the power budget. Other embodiments are also disclosed and claimed.