Eric Arthur Graf

US Patent:

6425094, Jul 23, 2002

Filed:

Aug 9, 1999

Appl. No.:

09/371059

Inventors:

Daniel P. Drogichen - Leucadia CA
Eric Eugene Graf - Hillsboro OR
Douglas B. Meyer - San Diego CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H02H 305

US Classification:

714 41, 714 11, 714 15, 714 30, 714 3, 712 30

Abstract:

A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers.

US Patent:

6571360, May 27, 2003

Filed:

Oct 19, 1999

Appl. No.:

09/422204

Inventors:

Daniel P. Drogichen - Leucadia CA
Eric Eugene Graf - Hillsboro OR
Don Kane - San Diego CA
Douglas B. Meyer - San Diego CA
Andrew E. Phelps - Encinitas CA
Patricia Shanahan - San Diego CA
Steven F. Weiss - San Diego CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 44, 714 40

Abstract:

A multiprocessing computer system provides the hardware support to properly test an I/O board while the system is running user application programs and while preventing a faulty board from causing a system crash. The system includes a centerplane that mounts multiple expander boards. Each expander board in turn connects a microprocessor board and an I/O board to the centerplane. Prior to testing, the replacement I/O board becomes a part of a dynamic system domain software partition after it has been inserted into an expander board of the multiprocessing computer system. Testing an I/O board involves executing a process using a microprocessor and memory on a microprocessor board to perform hardware tests on the I/O board. An error cage, address transaction cage, and interrupt transaction cage isolate any errors generated while the I/O board is being tested. The error cage isolates correction code errors, parity errors, protocol errors, timeout errors, and other similar errors generated by the I/O board under test.

US Patent:

6760868, Jul 6, 2004

Filed:

Jun 13, 2002

Appl. No.:

10/170928

Inventors:

Daniel P. Drogichen - Leucadia CA
Eric Eugene Graf - Hillsboro OR
Douglas B. Meyer - San Diego CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 1100

US Classification:

714 41, 714 11

Abstract:

A multiprocessor system is disclosed that employs an apparatus and method for caging a redundant component to allow testing of the redundant component without interfering with normal system operation. In one embodiment the multiprocessor system includes at least two system controllers and a set of processing nodes interconnected by a network. The system controllers allocate and configure system resources, and the processing nodes each include a node interface that couple the nodes to the system controllers. The node interfaces can be individually and separately configured in a caged mode and an uncaged mode. In the uncaged mode, the node interface communicates information from either of the system controllers to other components in the processing node. In the caged mode, the node interface censors information from at least one of the system controllers. When all node interfaces censor information from a common system controller, this system controller is effectively âcagedâ and communications from this system controller are thereby prevented from reaching other node components.

US Patent:

6877108, Apr 5, 2005

Filed:

Sep 25, 2001

Appl. No.:

09/963082

Inventors:

Donald Kane - San Diego CA, US
Steven Fitzgerald Weiss - San Diego CA, US
Eric E. Graf - Hillsboro OR, US
Andrew E. Phelps - Encinitas CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F011/00

US Classification:

714 4, 714 8

Abstract:

A method and apparatus for providing error isolation in a multi-domain computer system. The system includes a plurality of system resources allocated to form at least a first and second domain. The system resources of the first domain perform a set of transactions independent from a set of transactions performed by the system resources of the second domain. The system further comprises at least one interface for coupling one system resource from the first domain and one system resource from the second domain. The at least one interface tracks the set of transactions performed by the one system resource of the first domain and the one system resource of the second domain independently from one another.

US Patent:

7225363, May 29, 2007

Filed:

Mar 18, 2002

Appl. No.:

10/100536

Inventors:

Daniel P. Drogichen - Leucadia CA, US
Eric E. Graf - Hillsboro OR, US
James A. Gilbert - San Diego CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 11/00

US Classification:

714 39, 714 36

Abstract:

A method and apparatus for abandoning an interrupted task is provided. The method includes setting at least one of a plurality of logic elements associated with at least one of a plurality of first registers, wherein the plurality of first registers are adapted to access data stored in a plurality of second registers at substantially the same time when the plurality of logic elements are set. The method further includes resetting the plurality of logic elements substantially before the plurality of first registers access the data stored in the plurality of second registers.

US Patent:

7353418, Apr 1, 2008

Filed:

Mar 18, 2002

Appl. No.:

10/100127

Inventors:

Daniel P. Drogichen - Leucadia CA, US
Eric E. Graf - Hillsboro OR, US
James A. Gilbert - San Diego CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

H04L 7/02
H04L 7/04
H04L 7/10
H03K 5/14

US Classification:

713401, 713400, 713500, 713503, 327161, 327241

Abstract:

The present invention provides a method and apparatus for updating serial devices. The apparatus includes a plurality of serial registers. The apparatus further includes a device adapted to provide a signal and a plurality of parallel registers, wherein each of the parallel registers is adapted to access at least one of the plurality of serial registers at substantially the same time in response to detecting the signal.