Eric P Lewandowski

US Patent:

20130320529, Dec 5, 2013

Filed:

May 29, 2012

Appl. No.:

13/482414

Inventors:

Gregory M. Fritz - Yorktown Heights NY, US
Eric P. Lewandowski - White Plains NY, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H01L 23/498
H01L 21/30

US Classification:

257738, 438455, 257E21211, 257E23062

Abstract:

An array of bonding pads including a set of reactive materials is provided on a first substrate. The set of reactive materials is selected to be capable of ignition by magnetic heating induced by time-dependent magnetic field. The magnetic heating can be eddy current heating, hysteresis heating, and/or heating by magnetic relaxation processes. An array of solder balls on a second substrate is brought to contact with the array of bonding pads. A reaction is initiated in the set of magnetic materials by an applied magnetic field. Rapid release of heat during a resulting reaction of the set of reactive materials to form a reacted material melts the solder balls and provides boding between the first substrate and the second substrate. Since the magnetic heating can be localized, the heating and warpage of the substrate can be minimized during the bonding process.

US Patent:

20210305165, Sep 30, 2021

Filed:

Mar 31, 2020

Appl. No.:

16/835862

Inventors:

- Armonk NY, US
Eric Peter Lewandowski - White Plains NY, US
Nicholas Torleiv Bronn - Long Island City NY, US
Markus Brink - White Plains NY, US

International Classification:

H01L 23/538
G06N 10/00
H01L 29/66
H01L 23/498
H01L 23/00

Abstract:

Systems and techniques that facilitate hybrid readout packaging for quantum multichip bonding are provided. In various embodiments, an interposer can have a first quantum chip and a second quantum chip. In various aspects, a readout resonator (e.g., input/output port) of one or more qubits on the first quantum chip can be routed to an inner portion of the interposer. In various instances, the inner portion can be located between the first quantum chip and the second quantum chip. In various aspects, routing the readout resonator to the inner portion can reduce a number of crossings and/or intersections between input/output lines on the interposer and connection buses between qubits on the interposer.

US Patent:

20210159382, May 27, 2021

Filed:

Nov 27, 2019

Appl. No.:

16/698171

Inventors:

- Armonk NY, US
Li-Wen Hung - Mahopac NY, US
Eric P. Lewandowski - White Plains NY, US

International Classification:

H01L 39/06
H01L 39/24
G06N 10/00
H01L 39/04
H01L 27/18

Abstract:

A quantum device includes a qubit chip having a plurality of qubits and an interposer attached to and electrically connected to the qubit chip. The device also includes a substrate handler attached to one side of the qubit chip or to one side of the interposer, or both so as to be thermally in contact with the qubit chip or the interposer, or both. The substrate handler includes a plurality of vias, at least a portion of plurality of vias being filled with a non-superconducting material, the non-superconducting material being selected to dissipate heat generated in the qubit chip, the interposer or both.

US Patent:

20210118808, Apr 22, 2021

Filed:

Dec 9, 2020

Appl. No.:

17/116488

Inventors:

- Armonk NY, US
Eric Peter Lewandowski - White Plains NY, US

International Classification:

H01L 23/532
H01L 23/00
H01L 21/768

Abstract:

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

US Patent:

20210091372, Mar 25, 2021

Filed:

Sep 23, 2019

Appl. No.:

16/578461

Inventors:

- Armonk NY, US
Eric Peter Lewandowski - White Plains NY, US
Dana Alexa Totir - Sandy Hook CT, US

International Classification:

H01M 4/139
H01M 4/76
H01M 10/02
H01M 10/052
H01M 10/04
H01M 10/0585
H01M 4/04

Abstract:

A method of forming a thin film battery may include forming may include forming a trench in a substrate, depositing a stencil on top surface of the substrate, wherein the stencil is aligned with the trench, depositing a cathode layer in the trench, wherein the cathode layer is in direct contact with the stencil, and compressing the cathode layer into the trench to reduce a thickness of the cathode layer. The compressing the cathode layer into the trench may include applying isostatic pressure onto the cathode layer using a pressure head. The method may also include depositing an electrolyte layer on top of the cathode layer, depositing an anode layer on top of the electrolyte layer, and depositing an anode collector layer on top of the anode layer.

US Patent:

20200212475, Jul 2, 2020

Filed:

Jan 2, 2019

Appl. No.:

16/238159

Inventors:

- Armonk NY, US
Paul S. Andry - Yorktown Heights NY, US
Eric Peter Lewandowski - White Plains NY, US
Bucknell C. Webb - Yorktown Heights NY, US
Bo Wen - New York NY, US

International Classification:

H01M 10/04
H01M 4/505
H01M 4/66
H01M 2/02

Abstract:

Systems and/or techniques associated with a sandwich-parallel micro-battery are provided. In one example, a device comprises a first battery and a second battery. The first battery comprises a first surface and a second surface. The second surface is smaller than the first surface. The second battery comprises a third surface and a fourth surface. The fourth surface is smaller than the third surface. Furthermore, the fourth surface is mechanically coupled to the second surface of the first battery. The third surface of the second battery and the first surface of the first battery comprise a conductive contact that electrically couples the first battery and the second battery.

US Patent:

20200098695, Mar 26, 2020

Filed:

Sep 20, 2018

Appl. No.:

16/136808

Inventors:

- Armonk NY, US
Eric Peter Lewandowski - White Plains NY, US

International Classification:

H01L 23/532
H01L 23/00

Abstract:

Devices and methods that can facilitate hybrid under-bump metallization components are provided. According to an embodiment, a device can comprise an under-bump metallization component that can comprise a superconducting interconnect component and a solder wetting component. The device can further comprise a solder bump that can be coupled to the superconducting interconnect component and the solder wetting component. In some embodiments, the superconducting interconnect component can comprise a hermetically sealed superconducting interconnect component.

US Patent:

20190131510, May 2, 2019

Filed:

Dec 27, 2018

Appl. No.:

16/233852

Inventors:

- Armonk NY, US
John M. Cotte - New Fairfield CT, US
Eric P. Lewandowski - White Plains NY, US

International Classification:

H01L 39/04
H01L 23/00
H01L 39/24

Abstract:

A structure has a first substrate bonded to a first under-bump metallization (UBM) structure, the first UBM structure comprising a first bonding region laterally surrounded by a first superconducting region. A second substrate is bonded to a second under-bump metallization (UBM) structure, the second UBM structure comprising a second bonding region laterally surrounded by a second superconducting region; and a superconducting solder material joins the first UBM structure to the second UBM structure.