Eric Yi Lin

Address:

68 City Stroll, Irvine, CA 92620

Phone:

9495024079

VIN:

JTHKD5BH6C2096091

Make:

LEXUS

Model:

CT 200H

Year:

2012

US Patent:

7257134, Aug 14, 2007

Filed:

Oct 3, 2001

Appl. No.:

09/969702

Inventors:

James Ching-Shau Yik - Mission Viejo CA, US
Eric Lin - Hacienda Heights CA, US

Assignee:

Zarlink Semiconductor V.N. Inc. - Irvine CA

International Classification:

H04J 3/06
H04L 12/66
H04L 12/56
G06F 15/173

US Classification:

370509, 370352, 370389, 370511, 370503, 709223

Abstract:

A method of synchronizing the information held in a switching database associated with a switching function of a data switching node, with a data network node identifier record associated with a management processor enabling a managed mode thereof is provided. An entry of the switching database is modified. A status specifier corresponding to the modified entry is set to signify the modification thereof. An inspection of the switching database is initiated on the expiration of an adjustable timer, and the information held in modified switching database entries is synchronized with the data network node identifier record. This method of synchronization of the information held in the switching database spreads out of burst changes thereof over time. The advantages are derived from the use of a more economical management processor while providing the same or enhanced levels of service of the data switching node.

US Patent:

7260066, Aug 21, 2007

Filed:

Dec 20, 2002

Appl. No.:

10/326352

Inventors:

Linghsiao Wang - Irvine CA, US
Eric Lin - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US

Assignee:

Conexant Systems, Inc. - Red Bank NJ

International Classification:

G01R 31/08

US Classification:

370248, 370249

Abstract:

A method for actively detecting link failures on a high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. A probe packet is sent, and a probing timer is set whenever either a specified number of bad packets are received, or an idle timer expires. If a response to the probe packet is received before the probe timer expires then the link is deemed valid, otherwise the link is presumed to have failed. Preferably, either the node boards or the switch fabric boards are configured to properly handle a probe pack, which preferably has identical source and destination addresses.

US Patent:

7373425, May 13, 2008

Filed:

Dec 31, 2003

Appl. No.:

10/750445

Inventors:

Craig Barrack - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US
Eric Lin - Irvine CA, US

Assignee:

Conexant Systems, Inc. - Red Bank NJ

International Classification:

G06F 15/173
G06F 15/16

US Classification:

709238, 709245, 709247

Abstract:

Disclosed is an apparatus and method for storing and searching computer node addresses in a computer network system. In one embodiment, the apparatus comprises a frame forwarding device such as a switch. The switch includes two MAC address tables including a primary MAC address table and secondary MAC address table both for storing and searching MAC addresses. The primary table stores records that contain compressed values of MAC addresses. The records are contained in storage locations that are referenced using the compressed value of the MAC address as a search index. In order to account for searching collisions that may result from different MAC addresses compressing to the same value, each record in the primary address table is linked to a chain of records in the secondary table. The records in the secondary table store the full value of the MAC address. Each chain of records in the secondary address table contains MAC addresses the present invention.

US Patent:

7435132, Oct 14, 2008

Filed:

Dec 12, 2007

Appl. No.:

12/001688

Inventors:

Jen-Guo Fong - Tu-Cheng, TW
Eric (Yun-chien) Lin - Fullerton CA, US
Pei Tsao - Fullerton CA, US
Joseph Tang - Fullerton CA, US
An-Jen Yang - Fullerton CA, US
Tien-Lu Kao - Fullerton CA, US
Lisa Chou - Fullerton CA, US
Jim Zhao - Fullerton CA, US
Wei Yao - Kun-Shan, CN

Assignee:

Hon Hai Precision Ind. Co., Ltd. - Taipei Hsien

International Classification:

H01R 12/24

US Classification:

439497

Abstract:

A cable connector assembly () includes a printed circuit board () having a number of signal and ground pads () alternatively arranged at opposite front and rear ends thereof, a wire organizer () defining a number of through holes (), a unitary grounding member () assembled to the wire organizer and including a number of grounding plates () integrally formed therewith to electrically connect with the ground pads of the printed circuit board, and a number of wires () protruding through the through holes of the wire organizer. Each wire includes at least one signal conductor () soldered with the signal pad of the printed circuit board, an insulator () enclosing the at least one signal conductor and a ground conductor () electrically connecting with the grounding member to form ground path with the printed circuit board.

US Patent:

7497724, Mar 3, 2009

Filed:

Oct 4, 2007

Appl. No.:

11/906873

Inventors:

Jen-Guo Fong - Tu-Cheng, TW
Eric (YunChien) Lin - Fullerton CA, US
Pei Tsao - Fullerton CA, US
Joseph Tang - Fullerton CA, US
An-Jen Yang - Fullerton CA, US
Tien-Lu Kao - Fullerton CA, US
Lisa Chou - Fullerton CA, US
Jim Zhao - Fullerton CA, US
Wei Yao - Kun-Shan, CN

Assignee:

Hon Hai Precision Ind. Co., Ltd. - Taipei Hsien

International Classification:

H01R 12/24

US Classification:

439497, 439936

Abstract:

A cable connector assembly () in accordance with the present invention includes a printed circuit board () having a number of signal and ground pads () alternatively arranged at opposite front and rear ends () thereof, a conductive wire organizer () including a body portion () defining a number of through holes () and a number of ground plates () integrally extending forwardly from the body portion to electrically connecting with the ground pads of the printed circuit board, and a number of wires () protruding through the through holes of the wire organizer. Each wire includes at least one signal conductor () soldered with the signal pad of the printed circuit board, an insulator () enclosing the at least one signal conductor and a conductor layer () enclosing the insulator and electrically connecting with the wire organizer.

US Patent:

7760719, Jul 20, 2010

Filed:

Jun 30, 2004

Appl. No.:

10/881226

Inventors:

James Yik - Mission Viejo CA, US
Eric Lin - Irvine CA, US
John Ta - Laguna Niguel CA, US
Craig Barrack - Irvine CA, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H04L 12/28

US Classification:

370389, 370392, 37039542

Abstract:

A packet switching node in a pipelined architecture processing packets received via an input port associated with the packet switching node performs a method, which includes: determining a packet frame type; selectively extracting packet header field values specific to a packet frame type, including packet addressing information; ascribing to the packet a preliminary action to be performed; searching packet switching information tracked by the packet switching node based on extracted packet addressing information; formulating a preliminary switch response for the packet; classifying the packet into a packet flow; modifying the preliminary switch response in accordance with one of the preliminary action, the packet flow into which the packet was classified, and a default port action corresponding to the input port; modifying the packet header in accordance with one of the preliminary action, the packet flow, and the default port action; and processing the packet.

US Patent:

7813263, Oct 12, 2010

Filed:

Jul 30, 2004

Appl. No.:

10/903437

Inventors:

Eric Lin - Irvine CA, US
Craig Barrack - Irvine CA, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G01R 31/08
G06F 11/00

US Classification:

370216, 370225

Abstract:

A hardware-based failover scheme enabling rapid end-to-end recovery is provided. Hardware logic periodically generates, transmits, receives, and processes heartbeat packets, sent from one end of the communications network to another, and then returned back. If a communications network node or communications link failure is being experienced along the transport path, then the hardware logic rapidly swaps the affected traffic conveyed to a pre-established backup transport path, typically within microseconds. Advantages are derived from the rapid failover effected end-to-end which enables continued delivery of provisioned communications services improving the resiliency and/or availability of a communications network.

US Patent:

7835265, Nov 16, 2010

Filed:

Oct 31, 2002

Appl. No.:

10/284856

Inventors:

Linghsiao Wang - Irvine CA, US
Eric (Changhwa) Lin - Irvine CA, US
James Ching-Shau Yik - Mission Viejo CA, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 11/00
H04L 12/28

US Classification:

370216, 370245, 370248, 370338, 370392, 3703952, 709223, 709231, 709238, 709242

Abstract:

A high availability backplane architecture. The backplane system includes redundant node boards operatively communicating with redundant switch fabric boards. Uplink ports of the node boards are logically grouped into trunk ports at one end of the communication link with the switch fabric boards. The node boards and the switch fabric boards routinely perform link integrity checks when operating in a normal mode such that each can independently initiate failover to working ports when a link failure is detected. Link failure is detected either by sending a link heartbeat message after the link has had no traffic for a predetermined interval, or after receiving a predetermined consecutive number of invalid packets. Once the link failure is resolved, operation resumes in normal mode.