Eric N Paton

US Patent:

6342414, Jan 29, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/734189

Inventors:

Qi Xiang - San Jose CA
Paul R. Besser - Austin TX
Matthew S. Buynoski - Palo Alto CA
John C. Foster - Mountain View CA
Paul L. King - Mountain View CA
Eric N. Paton - Morgan Hill CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 218238

US Classification:

438201

Abstract:

A method for implementing a self-aligned low temperature metal silicide gate is achieved by confining a low temperature silicidation metal within a recess overlying a channel and annealing to cause the low temperature silicidation metal and its overlying silicon to interact to form the self-aligned low temperature metal silicide gate. A planarization step is performed to remove the remaining unreacted silicon by chemical mechanical polishing until no silicon is detected.

US Patent:

6368950, Apr 9, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/734186

Inventors:

Qi Xiang - San Jose CA
Paul R. Besser - Austin TX
Matthew S. Buynoski - Palo Alto CA
John C. Foster - Mountain View CA
Paul L. King - Mountain View CA
Eric N. Paton - Morgan Hill CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 438655, 438299, 438301, 438305

Abstract:

A method for implementing a self-aligned metal silicide gate is achieved by confining amorphous silicon within a recess overlying a channel and annealing to cause the amorphous silicon with its overlying metal to interact to form the self-aligned metal silicide gate. A gate dielectric layer formed of oxynitride or a nitride/oxide stack is formed on the bottom and sidewalls of the recess prior to depositing the silicon. The silicon is removed except for the portion of the silicon in the recess. The remaining portions of the metal are removed by manipulating the etch selectivity between the metal and the self-aligned metal silicide gate.

US Patent:

6387786, May 14, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/733778

Inventors:

Jeff Erhardt - San Jose CA
Eric Paton - Morgan Hill CA

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

H01L 21285

US Classification:

438586, 438303

Abstract:

The present invention relates to a method of forming a self-aligned silicide (salicide) by siliciding a gate area prior to siliciding a source and drain area and/or spacer formation. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area that is advantageously thicker than silicide formations over the source and drain areas.

US Patent:

6399467, Jun 4, 2002

Filed:

Dec 8, 2000

Appl. No.:

09/733779

Inventors:

Jeff Erhardt - San Jose CA
Eric Paton - Morgan Hill CA

Assignee:

Advanced Micro Devices - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 438655, 438664, 438683

Abstract:

A method of forming a self-aligned silicide (salicide) with a screening oxide. The method improves transistor speed by lowering the leakage current in the source and drain areas and lowering the polysilicon sheet resistance of the gate. As a result of one embodiment of the present method, a silicide is formed over the gate area which is advantageously about two to three times thicker than silicide formations over the source and drain areas.

US Patent:

6432805, Aug 13, 2002

Filed:

Feb 15, 2001

Appl. No.:

09/783620

Inventors:

Eric N. Paton - Morgan Hill CA
Minh Van Ngo - Fremont CA
Paul R. Besser - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 438299, 438303, 438652, 438683

Abstract:

Salicide processing is implemented with silicon nitride sidewall spacers by initially depositing a refractory metal, e. g. , Ni, in the presence of nitrogen to form a metal nitride layer to prevent the reaction of the deposited metal with free Si in silicon nitride sidewall spacers, thereby avoiding bridging between the metal silicide layer on the gate electrode and the metal silicide layers on the source/drain regions of a semiconductor device.

US Patent:

6458679, Oct 1, 2002

Filed:

Feb 12, 2001

Appl. No.:

09/780454

Inventors:

Eric N. Paton - Morgan Hill CA
Paul R. Besser - Austin TX
Matthew S. Buynoski - Palo Alto CA
Qi Xiang - San Jose CA
Paul L. King - Mountain View CA
John Clayton Foster - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 213205

US Classification:

438592, 438299

Abstract:

A damascene gate semiconductor structure that is formed utilizing a silicide stop layer. Initially, a gate opening is provided in an insulating layer on a substrate. A first dielectric layer is deposited in the gate opening over the substrate. A silicide stop layer is then deposited in the gate opening over the first silicon layer. A second silicon layer is then deposited in the gate opening over the silicide stop layer. A metal or alloy layer is then deposited over the insulating and the second silicon layer. The damascene semiconductor structure is then temperature treated to react the metal or alloy layer with the second silicon layer to form a silicide layer. Any unreated metal or alloy is then removed from the metal or alloy layer.

US Patent:

6465309, Oct 15, 2002

Filed:

Dec 12, 2000

Appl. No.:

09/734185

Inventors:

Qi Xiang - San Jose CA
Paul R. Besser - Austin TX
Matthew Buynoski - Palo Alto CA
John C. Foster - Mountain View CA
Paul L. King - Mountain View CA
Eric N. Paton - Morgan Hill CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438299, 438769, 438592, 438664

Abstract:

A semiconductor structure and method for making the same provides a gate dielectric formed of oxynitride or a nitride/oxide stack formed within a recess. Amorphous silicon is deposited on the gate dielectric within the recess and a metal is deposited on the amorphous silicon. An annealing process forms a metal silicide gate within the recess on the gate dielectric. A wider range of metal materials can be selected because the gate dielectric formed of oxynitride or a nitride/oxide stack remains stable during the silicidation process. The metal silicide gate significantly reduces the sheet resistance between the gate and gate terminal.

US Patent:

6465334, Oct 15, 2002

Filed:

Oct 5, 2000

Appl. No.:

09/679369

Inventors:

Matthew S. Buynoski - Palo Alto CA
Paul R. Besser - Austin TX
Paul L. King - Mountain CA
Eric N. Paton - Morgan Hill CA
Qi Xiang - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438591, 438299, 438300, 438301, 438592

Abstract:

High quality dielectric layers, e. g. , high-k dielectric layers comprised of at least one refractory or lanthanum series transition metal oxide or silicate, for use as gate insulator layers in in-laid metal gate MOS transistors and CMOS devices, are fabricated by forming an ultra-thin catalytic metal layer, e. g. , a monolayer thick layer of Pd or Pd, on a Si-based semiconductor substrate, electrolessly plating on the catalytic layer comprising at least one refractory or lanthanum series transition metal or metal-based dielectric precursor layer, such as of Zr and/or Hf, and then reacting the precursor layer with oxygen or with oxygen and the semiconductor substrate to form the at least one high-k metal oxide or silicate. The inventive methodology prevents, or at least substantially reduces, oxygen access to the substrate surface during at least the initial stage(s) of formation of the gate insulator layer, thereby minimizing deleterious formation of oxygen-induced surface states at the semiconductor substrate/gate insulator interface.