Eric Earl Pope

US Patent:

20220293207, Sep 15, 2022

Filed:

Mar 9, 2021

Appl. No.:

17/196758

Inventors:

- Houston TX, US
Eric L. Pope - Tomball TX, US

International Classification:

G11C 29/44

Abstract:

One embodiment provides a memory module that enables online repair of defective memory cells. The memory module includes a memory array storing data, a self-test controller coupled to the memory array and configured to perform a self-test on a region within the memory array without interrupting operations of the memory module, and a memory-repair module configured to repair a defective memory cell identified by the self-test controller.

US Patent:

20220284944, Sep 8, 2022

Filed:

Mar 2, 2021

Appl. No.:

17/189897

Inventors:

- Houston TX, US
Eric L. Pope - Tomball TX, US

International Classification:

G11C 11/4078
G11C 11/403

Abstract:

One embodiment provides a memory module. The memory module includes a plurality of rows of memory cells, with a respective row comprising one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells, and a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to the disturbance to the canary memory cell exceeding a predetermined threshold.

US Patent:

20210349836, Nov 11, 2021

Filed:

Jul 10, 2020

Appl. No.:

16/926628

Inventors:

- Houston TX, US
NIGEL EDWARDS - Bristol, GB
ERIC L. POPE - Houston TX, US

International Classification:

G06F 12/14
G06F 21/44

Abstract:

Systems and methods are provided for binding one or more components to an identification component of a hardware module. Each of the serial numbers for the one or more components are included within a module-specific authentication certificate that is stored within the identification component of the hardware module. When connected to a computing platform, an authentication system of the computing platform is capable of retrieving the module-specific authentication certificate. The authentication system can compare the list of serial numbers included in the module-specific authentication certificate with one or more serial numbers read over a first interface. If the two lists of serial numbers match, the authentication system can flag the hardware module as authenticate through authentication of all components of the hardware module.

US Patent:

20210349985, Nov 11, 2021

Filed:

May 8, 2020

Appl. No.:

16/870063

Inventors:

- Houston TX, US
ERIC L. POPE - Houston TX, US

International Classification:

G06F 21/44
G06F 13/16
G06F 13/42

Abstract:

Systems and methods are provided for a secondary authentication of a memory module. A nonce key is written to a nonce register of a register array on the memory module, the nonce register being accessible over two different interfaces. In various embodiments, the nonce key may be generated by a management system of the computing platform after performing one or more authentication processes for a memory module over a management interface. Authentication information for use in performing authentication can be stored in an identification component on the memory module. If authentication is successful, the management system can generate the nonce key and write it to the nonce register. Upon receiving a request to access an address, a memory controller can read the nonce register of the memory module at the requested address and compare the nonce key to an identifier included in the request.

US Patent:

20190026026, Jan 24, 2019

Filed:

Aug 28, 2015

Appl. No.:

15/752250

Inventors:

- Houston TX, US
Eric L POPE - Tomball TX, US

International Classification:

G06F 3/06

Abstract:

In one example in accordance with the present disclosure, a system for backup of a physical memory region of volatile memory. The system may include: a non-volatile memory, a volatile memory, at least one processor to: execute an application that indicates a virtual memory region stored in the volatile memory, wherein the virtual memory region is associated with an application, determine a corresponding physical memory region of the volatile memory for backup based on the indicated virtual memory region, and at least one memory controller to: receive a backup signal for the physical memory region of the volatile memory, and responsive to receiving the backup signal, backup up the physical memory region of the volatile memory to a memory region of the non-volatile memory.

US Patent:

20190019569, Jan 17, 2019

Filed:

Jan 28, 2016

Appl. No.:

16/066392

Inventors:

- Houston TX, US
Eric L Pope - Tomball TX, US

International Classification:

G11C 29/00
G11C 29/44
G11C 29/52
G11C 29/46

Abstract:

Addresses of memory cells that have errors corrected by error correction operations are evaluated to identify a failed row of memory. Post package repair is implemented on the failed row.

US Patent:

20180218763, Aug 2, 2018

Filed:

Feb 20, 2018

Appl. No.:

15/899514

Inventors:

- Houston TX, US
Melvin K. BENEDICT - Houston TX, US
Stephen F. CONTRERAS - Houston TX, US
Eric L. POPE - Houston TX, US
Chi K. SIDES - Houston TX, US
Chun-Pin HUANG - Taipei, TW

International Classification:

G11C 11/4074
G11C 5/06
G11C 5/10

Abstract:

An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

US Patent:

20170243626, Aug 24, 2017

Filed:

Feb 27, 2015

Appl. No.:

15/500070

Inventors:

- Houston TX, US
Melvin K. BENEDICT - Houston TX, US
Stephen F. CONTRERAS - Houston TX, US
Eric L. POPE - Houston TX, US
Chi K. SIDES - Houston TX, US
Chun-Pin HUANG - Taipei, TW

Assignee:

HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP - Houston TX

International Classification:

G11C 11/4074

Abstract:

An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.