Eric W Rasmussen

US Patent:

56762593, Oct 14, 1997

Filed:

Aug 18, 1995

Appl. No.:

8/517000

Inventors:

Michael Charchaflian - Worcester MA
Eric Rasmussen - Manchester NH

Assignee:

Automation & Information Planners Inc. - Worcester MA

International Classification:

A47F 708

US Classification:

211 34

Abstract:

A system for the storage and retrieval of pairs of boots utilizing a plurality of chutes, each having a diamond-shape cross section, with the chutes arranged in a honeycomb fashion, each chute having a carriage assembly disposed along the length of its inner apex. A plurality of hangers are provided, each having a pair of upwardly extending arms on which such pairs of boots can be mounted upside down with the hanger slideably and removably engaged to the carriage assembly. The chutes are disposed at a downward angle so that a pair of boots mounted on a hanger entered from the rear end of a chute will advance by gravity toward the front end of the chute where it can be removed when needed. An optional heating unit can be disposed on the bottom of each chute to speed up the drying time of the boots if such boots are wet.

US Patent:

20190171575, Jun 6, 2019

Filed:

Jan 31, 2019

Appl. No.:

16/264447

Inventors:

Wei CHEN - Portland OR, US
Larisa NOVAKOVSKY - Haifa, IS
Mark SCHMISSEUR - Phoenix AZ, US
Eric RASMUSSEN - Chelmsford MA, US
Stephen VAN DOREN - Portland OR, US
Yen-Cheng LIU - Portland OR, US

International Classification:

G06F 12/0891
G06F 12/02
G06F 12/0802

Abstract:

Techniques and mechanisms for capturing an image of processor state at one node of multiple nodes of a multi-processor platform, where the processor state includes some version of data which the node retrieved from another node of the platform. In an embodiment, a disruption of power is detected when a processor of a first node has a cached version of data which was retrieved from a second node. In response to detection of the disruption, the data is saved to a system memory of the first node as part of an image of the processor's state. The image further comprises address information, corresponding to the data, which indicates a memory location at the second node. In another embodiment, processor state is restored during a boot-up of the node, wherein the state includes the captured version of data which was previously retrieved from the second node.

US Patent:

20160364308, Dec 15, 2016

Filed:

Jun 12, 2015

Appl. No.:

14/737768

Inventors:

Vedvyas Shanbhogue - Austin TX, US
Eric Rasmussen - Chelmsford MA, US
Deep K. Buch - Folsom CA, US
Gordon McFadden - Hillsboro OR, US
Kameswar Subramaniam - Austin TX, US
Amy L. Santoni - Scottsdale AZ, US
Willard M. Wiseman - Tigard OR, US
Bret L. Toll - Hillsboro OR, US

International Classification:

G06F 11/263
G06F 11/22

Abstract:

In an embodiment, a processor includes at least one core, a power management unit having a first test register including a first field to store a test patch identifier associated with a test patch and a second field to store a test mode indicator to request a core functionality test, and a microcode storage to store microcode to be executed by the at least one core. Responsive to the test patch identifier, the microcode may access a firmware interface table and obtain the test patch from a non-volatile storage according to an address obtained from the firmware interface table. Other embodiments are described and claimed.