Eric S Robinson

US Patent:

8296520, Oct 23, 2012

Filed:

Dec 19, 2007

Appl. No.:

11/959652

Inventors:

Hien Minh Le - Cedar Park TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Richard Nicholas - Round Rock TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/08

US Classification:

711124, 711121, 711135, 711143

Abstract:

A method for managing data operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache comprising a plurality of cache lines, each cache line having one of a plurality of coherency states, and each PU coupled to at least another one of the plurality of PUs. A first PU selects a castout cache line of a plurality of cache lines in a first cache of the first PU to be castout of the first cache. The first PU sends a request to a second PU, wherein the second PU is a neighboring PU of the first PU, and the request comprises a first address and first coherency state of the selected castout cache line. The second PU determines whether the first address matches an address of any cache line in the second PU. The second PU sends a response to the first PU based on a coherency state of each of a plurality of cache lines in the second cache and whether there is an address hit. The first PU determines whether to transmit the castout cache line to the second PU based on the response.

US Patent:

8397029, Mar 12, 2013

Filed:

Dec 19, 2007

Appl. No.:

11/959793

Inventors:

Richard Nicholas - Round Rock TX, US
Jason Alan Cox - Raleigh NC, US
Robert John Dorsey - Durham NC, US
Hien Minh Le - Cedar Park TX, US
Eric Francis Robinson - Raleigh NC, US
Thuong Quang Truong - Austin TX, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 12/00

US Classification:

711141, 711118, 711119, 711122, 711124, 711144, 711145, 711146, 711154

Abstract:

A method for maintaining cache coherency operates in a data processing system with a system memory and a plurality of processing units (PUs), each PU having a cache, and each PU coupled to at least another one of the plurality of PUs. A first PU receives a first data block for storage in a first cache of the first PU. The first PU stores the first data block in the first cache. The first PU assigns a first coherency state and a first tag to the first data block, wherein the first coherency state is one of a plurality of coherency states that indicate whether the first PU has accessed the first data block. The plurality of coherency states further indicate whether, in the event the first PU has not accessed the first data block, the first PU received the first data block from a neighboring PU.

US Patent:

20200065247, Feb 27, 2020

Filed:

Aug 27, 2018

Appl. No.:

16/113185

Inventors:

- San Diego CA, US
David Scott RAY - Austin TX, US
Thomas Philip SPEIER - Wake Forest NC, US
Eric ROBINSON - Raleigh NC, US
Nikhil Narendradev SHARMA - Apex NC, US
Joseph Gerald MCDONALD - Raleigh NC, US
Brian Michael STEMPEL - Raleigh NC, US
Garrett Michael DRAPALA - Cary NC, US

International Classification:

G06F 12/0862
G06F 12/0811

Abstract:

An apparatus, method, and system for memory bandwidth aware data prefetching is presented. The method may comprise monitoring a number of request responses received in an interval at a current prefetch request generation rate, comparing the number of request responses received in the interval to at least a first threshold, and adjusting the current prefetch request generation rate to an updated prefetch request generation rate by selecting the updated prefetch request generation rate from a plurality of prefetch request generation rates, based on the comparison. The request responses may be NACK or RETRY responses. The method may further comprise either retaining a current prefetch request generation rate or selecting a maximum prefetch request generation rate as the updated prefetch request generation rate in response to an indication that prefetching is accurate.

US Patent:

20170371783, Dec 28, 2017

Filed:

Jun 24, 2016

Appl. No.:

15/191686

Inventors:

- San Diego CA, US
Thuong Quang Truong - Austin TX, US
Eric Francis Robinson - Raleigh NC, US
Brad Herold - Austin TX, US
Robert Bell, JR. - Raleigh NC, US

International Classification:

G06F 12/084
G06F 12/0842

Abstract:

Self-aware, peer-to-peer cache transfers between local, shared cache memories in a multi-processor system is disclosed. A shared cache memory system is provided comprising local shared cache memories accessible by an associated central processing unit (CPU) and other CPUs in a peer-to-peer manner. When a CPU desires to request a cache transfer (e.g., in response to a cache eviction), the CPU acting as a master CPU issues a cache transfer request. In response, target CPUs issue snoop responses indicating their willingness to accept the cache transfer. The target CPUs also use the snoop responses to be self-aware of the willingness of other target CPUs to accept the cache transfer. The target CPUs willing to accept the cache transfer use a predefined target CPU selection scheme to determine its acceptance of the cache transfer. This can avoid a CPU making multiple requests to find a target CPU for a cache transfer.

Address:

1023 Lott Ave, Austin, TX 78721

VIN:

5NMSG13D37H086035

Make:

HYUNDAI

Model:

SANTA FE

Year:

2007