Schneider Electric - Fort Collins, Colorado Area since 2009
Sr. Design Engineer
Integral technologies 2005 - 2009
Sr Design Engineer
Pelco - Indianapolis, Indiana Area 2005 - 2009
Senior Design Engineer
Truevision/Pinnacle 1989 - 2003
Scientist
Education:
University of Michigan 1979 - 1984
PhD, Physics
Skills:
Embedded Systems C Software Engineering Semiconductors C++ Electronics Software Development Linux Vhdl Embedded Software Fpga Firmware Asic Engineering Management Product Marketing Software Design Hardware Architecture Programming Algorithms Field Programmable Gate Arrays Application Specific Integrated Circuits
Sep 2012 to 2000 Founder of Logic IngenuitySchneider Electric
Nov 2004 to Jul 2012 Principal Engineer Integral Technologies/PelcoPinnacle Systems Indianapolis, IN Apr 1989 to Oct 2004 ScientistMTS Bell Laboratories Murray Hill, NJ Sep 1984 to Mar 1989 Design of cache controller in ECLPost Doctorate Fellowship University of Michigan
Mar 1984 to Aug 1984Graduate Research University of Michigan
Aug 1979 to Feb 1984Undergraduate Research Indiana University
Aug 1973 to Jul 1979
Education:
University of Michigan 1984 PhD in PhysicsIndiana University 1979 BS in Physics
Us Patents
Method And Apparatus For Achieving Active Noise Reduction
A system and method for actively changing the sound perceived by listeners in an audio environment. A single transducer is used as both a sensing microphone and as an output driver. In one embodiment, the invention is implemented as an active noise cancellation system. The sensed noise signals are phase shifted to provide a cancellation effect, combined with the desired audio program signals, and output to the transducer, thereby reducing the level of unwanted noise heard by they listener. In other embodiments, the system can be used to sense the frequency response of a listening room and make appropriate equalization adjustments to the output.
Victor J. Duvanenko - Indianapolis IN Eric Shumard - Indianapolis IN
Assignee:
Truevision, Inc. - Santa Clara CA
International Classification:
G06F 738
US Classification:
708290
Abstract:
An interpolated lookup table circuit includes an input port for receiving an input signal having a first plurality of bits (N bits) including a first portion (Q bits) and a second portion (N-Q bits), a lookup table (LUT) having a plurality of entries wherein each of the plurality of entries has a second plurality of bits including a third portion (V bits) and a fourth portion (D bits), selection means operatively coupled to the input port and responsive to at least the first portion of the input signal which selects one of the plurality of LUT entries based on the first portion of the lookup table input signal. The interpolated LUT circuit also includes a combiner operatively coupled to the input port and the LUT wherein the combiner combines the second portion of the input signal, the fourth portion of the selected LUT entry, and the third portion of the second plurality of bits of the selected LUT entry to provide an interpolated LUT output signal which is input to a rounding circuit wherein the interpolated LUT output signal is rounded or truncated to provide a rounded interpolated LUT output signal.