Erik W Buehler

US Patent:

20220271830, Aug 25, 2022

Filed:

Feb 9, 2022

Appl. No.:

17/668177

Inventors:

- Centennial CO, US
Erik Buehler - Castle Rock CO, US
Damon Van Buren - Parker CO, US

International Classification:

H04B 7/185
H04B 1/00
H04B 7/08
H04B 7/212
H04B 1/44
H04B 1/40

Abstract:

An integrated analog to digital converting and digital to analog converting (ADDA) RF transceiver for satellite applications, configured to replace conventional analog RF down and up conversion circuitry. The ADDA RF transceiver includes one of more ADCs, DSPs, and DACs, all on a single ASIC. Further, the circuitry is to be radiation tolerant for high availability and reliability in the ionizing radiation environment present in the space environment.

US Patent:

20170264360, Sep 14, 2017

Filed:

Mar 10, 2017

Appl. No.:

15/456086

Inventors:

- Centennial CO, US
ERIK BUEHLER - CASTLE ROCK CO, US

International Classification:

H04B 7/185
H04B 1/04
H04B 7/08
H04B 7/06

Abstract:

A satellite communication system processes a plurality of input signals to generate beamformed signals, drives a plurality of nonlinear power amplifiers with the beamformed input signals to produce RF signals for transmission; and transmits the RF signals with a plurality of Tx antenna elements. Conversion to and from linear signals to and from nonlinear or digitized signals is performed. Temporal or spatial decorrelation of the beamformed signals is employed to reduce the impact of intermodulation products. In some cases the power amplifiers are nonlinear, and can be one-sided or two-sided and produce two or three distinct output levels.

US Patent:

20160188395, Jun 30, 2016

Filed:

Jul 29, 2015

Appl. No.:

14/812871

Inventors:

- Centennial CO, US
ERIK BUEHLER - CASTLE ROCK CO, US

International Classification:

G06F 11/07

Abstract:

Light-weight, configurable error detection in a satellite communication system that detects invalid SerDes lanes via hash codes appended to packets of data in the lanes. An indication can be passed back upstream about the invalid lane so that the lane can be reset. Error correction can be provided by reconstructing the bit data in the invalid SerDes lane based on parity information in an optional parity lane.