Erin K Jones

US Patent:

6406962, Jun 18, 2002

Filed:

Jan 17, 2001

Appl. No.:

09/761931

Inventors:

Paul D. Agnello - Wappingers Falls NY
Arne W. Ballantine - Round Lake NY
Ramachandra Divakaruni - Somers NY
Erin C. Jones - Tuckahoe NY
Edward J. Nowak - Essex Junction VT
Jed H. Rankin - S. Burlington VT

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 21336

US Classification:

438268, 438284, 438270

Abstract:

The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable gate lengths. The present invention provides for control and formation of gate lengths scaled down to about 5 nm to about 100 nm, preferably from about 5 nm to about 50 nm. The plurality of pad nitride layers with the oxide etch-stop layers provide for the present FET to be connected to a plurality of contacts having a variety of connection depths corresponding to the gate lengths used, by etching a plurality of via in the pad nitride layers whereby such vias stop at selected ones of the etch-stop layers to provide vias adapted to connect with the selected ones of such contacts. Additional gate material may be deposited over a top surface of the selected plurality of nitride layers to allow for contacts to the gate electrodes of any given FET.

US Patent:

6833569, Dec 21, 2004

Filed:

Dec 23, 2002

Appl. No.:

10/328234

Inventors:

Omer H. Dokumaci - Wappingers Falls NY
Bruce B. Doris - Brewster NY
Suryanarayan G. Hegde - Hollowville NY
Meikei Ieong - Wappingers Falls NY
Erin C. Jones - Corvallis OR

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27148

US Classification:

257250, 257270, 257302, 257328, 438156, 438268, 438283

Abstract:

The present invention provides a method for fabricating a planar DGFET having a back gate that is aligned to a front gate. The method of the present invention achieves this alignment by creating a carrier-depleted zone in portions of the back gate. The carrier-depleted zone reduces the capacitance between the source/drain regions and the back gate thereby providing a high-performance self-aligned planar double-gate field effect transistor (DGFET). The present invention also provides a planar DGFET having a back gate that is aligned with the front gate. The front to back gate alignment is achieved by providing a carrier-depleted zone in portions of the back gate.

US Patent:

7205185, Apr 17, 2007

Filed:

Sep 15, 2003

Appl. No.:

10/663471

Inventors:

Omer H. Dokumaci - Wappingers Falls NY, US
Bruce B. Doris - Brewster NY, US
Kathryn W. Guarini - Yorktown Heights NY, US
Suryanarayan G. Hegde - Hollowville NY, US
MeiKei Ieong - Wappingers Falls NY, US
Erin Catherine Jones - Corvallis OR, US

Assignee:

International Busniess Machines Corporation - Armonk NY

International Classification:

H01L 21/336
H01L 21/8234

US Classification:

438197, 438199, 438217, 438289, 257250, 257365

Abstract:

A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.

US Patent:

7453123, Nov 18, 2008

Filed:

Feb 16, 2007

Appl. No.:

11/676030

Inventors:

Omer H. Dokumaci - Wappingers Falls NY, US
Bruce B. Doris - Brewster NY, US
Kathryn W. Guarini - Yorktown Heights NY, US
Suryanarayan G. Hegde - Hollowville NY, US
Meikei Ieong - Wappingers Falls NY, US
Erin Catherine Jones - Corvallis OR, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/01

US Classification:

257347, 257250, 257366, 257E21623, 257E29275

Abstract:

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer: a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

US Patent:

7960790, Jun 14, 2011

Filed:

May 13, 2008

Appl. No.:

12/119765

Inventors:

Omer H. Dokumaci - Wappingers Falls NY, US
Bruce B. Doris - Brewster NY, US
Kathryn W. Guarini - Yorktown Heights NY, US
Meikei Ieong - Wappingers Falls NY, US
Erin Catherine Jones - Corvallis OR, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 27/01

US Classification:

257347, 257365, 257366, 257368, 257E27112, 257E29264, 257E29275

Abstract:

A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.

US Patent:

20020197836, Dec 26, 2002

Filed:

Jun 11, 2001

Appl. No.:

09/878556

Inventors:

S. Sundar Iyer - Beacon NY, US
Suryanarayan Hegde - Hollowville NY, US
Erin Jones - Tuckahoe NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L021/3205
H01L021/336
H01L021/4763

US Classification:

438/585000, 438/279000, 438/981000

Abstract:

A method for forming variable oxide thicknesses across semiconductor chips comprises providing a silicon semiconductor substrate having pre-selected areas open to silicon surface using a photoresist layer; immersing the silicon semiconductor substrate in an HF type electrolytic bath to produce a porous silicon area; and removing the photoresist layer and oxidizing the silicon semiconductor substrate to produce a plurality of thicknesses of gate oxide on the silicon semiconductor substrate.