Ernest I Allen

US Patent:

54935199, Feb 20, 1996

Filed:

Aug 16, 1993

Appl. No.:

8/107385

Inventors:

Ernest Allen - Santa Cruz CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 1900
G06F 1700

US Classification:

364579

Abstract:

A circuit that provides for digitally programmable high voltage drive, as well as fast current limiting capability for testing of integrated circuits. The circuit also provides for digitally programmable slew rate control for controlling the rise and fall times of an output voltage. Integrated circuits requiring low voltage and high voltage tests at different speeds and with different current limiting conditions, or low and high current forcing with different voltage clamp levels, or a mixture of the two can be tested in a single continuous test pattern using the circuit of the present invention.

US Patent:

61347035, Oct 17, 2000

Filed:

Dec 23, 1997

Appl. No.:

8/996530

Inventors:

Ernest Allen - Hillsboro OR

Assignee:

Lattice Semiconductor Corporation - Hillsboro OR

International Classification:

G06F 1750
H03K 17693

US Classification:

716 16

Abstract:

A process for efficiently programming a programmable logic device (PLD) is provided. A basis set for a desired matrix of programming pattern ("pattern matrix") is a set of row patterns from which all the row patterns of the pattern matrix can be derived by applying a Boolean operation on two or more row patterns of the basis set. The disclosed process derives a minimal basis set, i. e. , a set with the smallest number of row patterns among basis sets for the given pattern matrix.

US Patent:

56213123, Apr 15, 1997

Filed:

Jul 5, 1995

Appl. No.:

8/498190

Inventors:

Alan Achor - Cupertino CA
Eric F. H. Chun - San Jose CA
Ernest Allen - Hillsboro OR

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3102

US Classification:

3241581

Abstract:

A method and apparatus for checking the integrity of a device tester used in the manufacture of semiconductor devices. A device tester is used to exercise different aspects of a semiconductor device. The tester is programmed with appropriate control software that fully tests the electrical and functional characteristics of the semiconductor device.

US Patent:

56083378, Mar 4, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/481744

Inventors:

Matthew C. Hendricks - Palo Alto CA
Ernest Allen - Hillsboro OR

Assignee:

Altera Corporation - San Jose CA

International Classification:

G01R 3128

US Classification:

324765

Abstract:

A method and apparatus for testing an integrated circuit device. An integrated circuit device undergoes testing in at least two different stages of the manufacturing process. At one stage, the semiconductor wafer containing multiple chip dice is probed by a probe tester that tests each of the dice individually. At another stage, after an individual chip die has been encapsulated in a package, a package tester tests and exercises the functions of the chip.