Esther Shu Jeng

US Patent:

20130171822, Jul 4, 2013

Filed:

Feb 22, 2013

Appl. No.:

13/774350

Inventors:

Anand Chandrashekar - Sunnyvale CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768

US Classification:

438675, 118696

Abstract:

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

US Patent:

20130302980, Nov 14, 2013

Filed:

Mar 27, 2013

Appl. No.:

13/851885

Inventors:

Anand Chandrashekar - Sunnyvale CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768

US Classification:

438666

Abstract:

Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

US Patent:

20130005140, Jan 3, 2013

Filed:

Jun 28, 2012

Appl. No.:

13/536095

Inventors:

Esther Jeng - Los Altos CA, US
Anand Chandrashekar - Fremont CA, US
Raashina Humayun - Fremont CA, US
Michal Danek - Cupertino CA, US
Ronald Powell - Portola Valley CA, US

Assignee:

Novellus Systems, Inc. - San Jose CA

International Classification:

H01L 21/768
H01L 21/306

US Classification:

438653, 15634524, 15634526, 257E21584, 257E21585

Abstract:

A method for filling a recessed feature of a substrate includes a) at least partially filling a recessed feature of a substrate with tungsten-containing film using at least one of chemical vapor deposition (CVD) and atomic layer deposition (ALD); b) at a predetermined temperature, using an etchant including activated fluorine species to selectively etch the tungsten-containing film more than an underlying material of the recessed feature without removing all of the tungsten-containing film at a bottom of the recessed feature; and c) filling the recessed feature using at least one of CVD and ALD.

US Patent:

20230041794, Feb 9, 2023

Filed:

Jun 28, 2022

Appl. No.:

17/809480

Inventors:

- Fremont CA, US
Esther JENG - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal DANEK - Cupertino CA, US
Juwen GAO - San Jose CA, US
Deqi WANG - San Jose CA, US

International Classification:

H01L 21/768
H01L 27/108
C23C 16/04
C23C 16/06
H01L 21/285
H01L 21/321

Abstract:

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

US Patent:

20210327754, Oct 21, 2021

Filed:

Jun 25, 2021

Appl. No.:

17/359068

Inventors:

- Fremont CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768
H01L 21/285
H01L 27/105
H01L 27/108
C23C 16/04
H01L 21/3213

Abstract:

Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).

US Patent:

20200185273, Jun 11, 2020

Filed:

Feb 18, 2020

Appl. No.:

16/793464

Inventors:

- Fremont CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768
C23C 16/00
C23C 16/50
C23C 16/04
H01L 27/11556
H01L 27/11524
H01L 21/324
H01L 21/321
H01L 21/285

Abstract:

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. Pre-inhibition and post-inhibition treatments are used to modulate the inhibition effect, facilitating feature fill using inhibition across a wide process window. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate and wordline fill, and 3-D integration using through-silicon vias.

US Patent:

20190206731, Jul 4, 2019

Filed:

Mar 6, 2019

Appl. No.:

16/294736

Inventors:

- Fremont CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768
C23C 16/06
C23C 16/04
H01L 21/285
H01L 21/321
H01L 27/108

Abstract:

Described herein are methods of filling features with tungsten, and related systems and apparatus, involving inhibition of tungsten nucleation. In some embodiments, the methods involve selective inhibition along a feature profile. Methods of selectively inhibiting tungsten nucleation can include exposing the feature to a direct or remote plasma. In certain embodiments, the substrate can be biased during selective inhibition. Process parameters including bias power, exposure time, plasma power, process pressure and plasma chemistry can be used to tune the inhibition profile. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) wordlines. The methods may be used for both conformal fill and bottom-up/inside-out fill. Examples of applications include logic and memory contact fill, DRAM buried wordline fill, vertically integrated memory gate/wordline fill, and 3-D integration using through-silicon vias.

US Patent:

20190019725, Jan 17, 2019

Filed:

Sep 6, 2018

Appl. No.:

16/124050

Inventors:

- Fremont CA, US
Esther Jeng - Los Altos CA, US
Raashina Humayun - Los Altos CA, US
Michal Danek - Cupertino CA, US
Juwen Gao - San Jose CA, US
Deqi Wang - San Jose CA, US

International Classification:

H01L 21/768
H01L 27/108
C23C 16/04
H01L 27/105
H01L 21/285
H01L 21/3213
H01L 21/321

Abstract:

Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).