Eugene Y Ho

US Patent:

7315910, Jan 1, 2008

Filed:

Jun 16, 2005

Appl. No.:

11/156318

Inventors:

Wilson Wai Shun Chan - San Mateo CA, US
Angelo Pruscino - Los Altos CA, US
Stefan Roesch - San Mateo CA, US
Michael Zoll - Redwood City CA, US
Tolga Yurek - Foster City CA, US
Eugene Ho - San Ramon CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 12/14
G06F 7/00
G06F 11/00
G06F 9/46

US Classification:

710200, 707 8, 714 2, 714 25, 714 47, 718105

Abstract:

Techniques are described herein for handling lock-related inconsistencies. As mentioned above, such inconsistencies occur when two or more sets of lock information, relating to the same resource, convey inconsistent information about locks requested and/or granted on that resource. In general, the techniques involve causing the locally-stored lock information about a resource to be sent to the master node of the resource. The master node of the resource compares the lock information thus received against the lock information maintained by the master node. Based on the comparison, the master node determines how to resolve the lock-related inconsistency, and sends messages to those nodes that need to change their local lock information for the resource. Once all of the lock information has been made consistent, the resource made available for access.

US Patent:

7535242, May 19, 2009

Filed:

May 3, 2006

Appl. No.:

11/417964

Inventors:

Bret Stott - Menlo Park CA, US
Philip Yeung - Mountain View CA, US
John W. Brooks - San Jose CA, US
Benedict Lau - San Jose CA, US
Chanh V. Tran - San Jose CA, US
Eugene C. Ho - San Jose CA, US

Assignee:

Rambus Inc. - Los Altos CA

International Classification:

G01R 31/26

US Classification:

324763

Abstract:

An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.

US Patent:

7600063, Oct 6, 2009

Filed:

Sep 15, 2006

Appl. No.:

11/521908

Inventors:

Juan Loaiza - Woodside CA, US
Neil MacNaughton - Los Gatos CA, US
Eugene Ho - San Ramon CA, US
Vipin Gokhale - Fremont CA, US
Kiran Goyal - Foster City CA, US
Tirthankar Lahiri - Palo Alto CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 12/00

US Classification:

710200, 710240, 711150

Abstract:

Techniques are provided for performing changes to a resource governed by a locking mechanism. An entity (such as a server instance in a database system cluster) requests permission to modify the resource. In response to the request, the entity receives a first lock on the resource, which grants permission to perform the change to the resource without making the change permanent. After receiving the first lock, the entity performs the change to a copy of the resource that resides in shared memory without making another copy of the resource. After performing the change and until receiving permission to make the change permanent, the entity prevents the change to the resource from becoming permanent. After performing the change, the entity receives a second lock on the resource, which grants the entity permission to make the change permanent. After receiving the second lock, the entity ceases to prevent the change to the resource from becoming permanent.

US Patent:

7915912, Mar 29, 2011

Filed:

Sep 9, 2009

Appl. No.:

12/555886

Inventors:

Kyung Suk Oh - Cupertino CA, US
Woopoung Kim - Dallas TX, US
Huy M. Nguyen - San Jose CA, US
Eugene C. Ho - Saratoga CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 36518909

Abstract:

Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

US Patent:

7921090, Apr 5, 2011

Filed:

Jun 9, 2006

Appl. No.:

11/450179

Inventors:

Eugene Ho - San Ramon CA, US
Kotaro Ono - Foster City CA, US
Neil Macnaughton - Los Gatos CA, US
Michael Zoll - Mountain View CA, US
Herbert van den Bergh - Los Altos CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 17/00
G06F 7/00
G06F 15/16

US Classification:

707704, 707705, 709210

Abstract:

Methods and apparatuses for providing access to data in a cluster database are described. Embodiments of the invention include identifying situations in which many nodes require relatively equal access to a data block, and taking appropriate measures to improve the performance of the system in these situations. For example, a node may automatically downgrade its lock from an X lock to an S lock as soon as it has finished a modification of the data. S locks are sent to other nodes in the system as soon as a modification is complete. Modifications to the data are also sent to other nodes in the system as soon as a modification is complete. Depending on the size of the data modification, the entire data block may be sent, or only the modifications to the data may be sent.

US Patent:

8103642, Jan 24, 2012

Filed:

Feb 3, 2006

Appl. No.:

11/346822

Inventors:

Eugene Ho - San Ramon CA, US
Wilson Wai Shun Chan - San Mateo CA, US
Tak Fung Wang - Redwood City CA, US
Angelo Pruscino - Los Altos CA, US
Tolga Yurek - Foster City CA, US

Assignee:

Oracle International Corporation - Redwood Shores CA

International Classification:

G06F 7/00
G06F 17/00
G06F 15/173

US Classification:

707704, 707650, 707653, 709225

Abstract:

A method and apparatus for managing locks in a database system is provided. A master node grants a lock on a first resource and a group of resources that includes the first resource to a first requester node. The requester node receives a mapping corresponding to the group of resources that may indicate that a lock already exists for a second resource in the group. If the requester node desires a lock on a resource located in the group, the requester node grants itself the lock without notifying the master node. A second requester node requests a lock for a particular resource in the group of resources. The first requester node grants the lock on the particular resource and updates the mapping to indicate that a different node holds a lock for the particular resource.

US Patent:

8130010, Mar 6, 2012

Filed:

Feb 7, 2011

Appl. No.:

13/022539

Inventors:

Kyung Suk Oh - Cupertino CA, US
Woopoung Kim - Dallas TX, US
Huy M. Nguyen - San Jose CA, US
Eugene C. Ho - Saratoga CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

H03K 17/16
H03K 19/003

US Classification:

326 30, 36518909

Abstract:

Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

US Patent:

8378699, Feb 19, 2013

Filed:

Apr 27, 2009

Appl. No.:

12/430832

Inventors:

Bret Stott - Menlo Park CA, US
Philip Yeung - Los Altos CA, US
John W. Brooks - San Jose CA, US
Benedict Lau - San Jose CA, US
Chanh V. Tran - San Jose CA, US
Eugene C. Ho - San Jose CA, US

Assignee:

Rambus Inc. - Sunnyvale CA

International Classification:

G01R 31/20
G01R 31/26

US Classification:

32475407, 32476201

Abstract:

An integrated circuit is described. The integrated circuit includes an interface circuit that includes a transmitter and a receiver. A generator in the integrated circuit is selectively coupled to the transmitter. The generator is to provide a test sequence that is output by the transmitter during a test mode of operation. A memory in the integrated circuit is selectively coupled to the generator and the receiver. The memory is to receive and synchronize the test sequence and a signal corresponding to the test sequence that is received by the receiver. A logic circuit in the integrated circuit is to compare the test sequence and the signal.