Eugene D Thomas

US Patent:

56066660, Feb 25, 1997

Filed:

Jul 19, 1994

Appl. No.:

8/277394

Inventors:

Carl H. Grant - Boca Raton FL
Jace W. Krull - Boca Raton FL
Charles E. Kuhlmann - Boca Raton FL
Shahram Salamian - Austin TX
Eugene M. Thomas - Clermont FL
James T. Tsevdos - Ft. Lauderdale FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300

US Classification:

39520008

Abstract:

A computer system is provided in which asynchronously operating processing elements in the system are connected by means of an interconnection media so as to permit communication between an executing program on one of the processing elements with the memory on another processing element. Inter-processing communication logic located on each of the processing elements permits communication between executing programs on any one processing element. Inter-delivery support hardware is provided for interfacing between the interconnection media and the inter-processing communication logic. The inter-delivery support hardware operates asynchronously with respect to the executing programs on the processing elements for (i) enqueuing control elements obtained by a function on a first processing element from physical memory on the first processing element; (ii) temporarily storing the enqueued control elements in a first memory device associated with the first processing element; (iii) copying over the interconnection media via a copy transaction the temporarily stored control elements from the first memory device to a second memory device associated with a second processing element; and (iv) dequeuing the copied control elements from the second memory device to physical memory on the second processing element.

US Patent:

53254929, Jun 28, 1994

Filed:

Jun 11, 1993

Appl. No.:

8/076081

Inventors:

Francis M. Bonevento - Boca Raton FL
Joseph P. McGovern - Boca Raton FL
Eugene M. Thomas - Boca Raton FL

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1338

US Classification:

395325

Abstract:

A microprocessor system includes a processor unit, one or more subsystem adapter units, optional I/O devices which may attach to the adapters, and a bus interface. Memory in the processor and memory in the adapters are used by the system as a shared memory which is configured as a distributed First In First Out (FIFO) circular queue (a pipe). Unit to unit asynchronous communication is accomplished by placing self-describing control elements on the pipe which represent requests, replies, and status information. The units send and receive self-describing control elements independent of the other units which allows free flowing asynchronous delivery of control information and data between units. The distributed, shares memory can be organized as pipe pairs between each pair of units to allow full duplex operation by using one pipe for outbound control elements and the other pipe for inbound control elements. The control elements have standard fixed header fields with variable fields following the fixed header.