Ewan D Milne

US Patent:

7032108, Apr 18, 2006

Filed:

May 2, 2003

Appl. No.:

10/428682

Inventors:

Justin Maynard - Groton MA, US
Ewan Milne - Stow MA, US
Robert Oakes - Somerville MA, US

Assignee:

Egenera, Inc. - Marlboro MA

International Classification:

G06F 15/177
G06F 9/00
G06F 9/24
G06F 9/455

US Classification:

713 2, 713 1, 713100

Abstract:

A system and method to virtualize BIOS, including run time services. A processing system has a processor, a memory system with a predefined physical address space, a storage medium, and a communication medium between the processor and the storage medium. The processing system is operable in a pre-execution environment in which a specified portion of the physical address space is used to map basic input/output system (BIOS) run time service routines. The specified portion contains RAM memory. A BIOS virtualization system includes an image of the BIOS processor-executable instructions on the storage medium and processor-executable instructions that retrieve the BIOS image from the storage medium and store the BIOS image into the RAM memory mapped into the second specified portion of physical address space.

US Patent:

7174390, Feb 6, 2007

Filed:

Jan 4, 2002

Appl. No.:

10/038354

Inventors:

Peter Schulter - Hampstead NH, US
Scott Geng - Westboro MA, US
Pete Manca - Sterling MA, US
Paul Curtis - Sudbury MA, US
Ewan Milne - Stow MA, US
Max Smith - Natick MA, US
Alan Greenspan - Northboro MA, US
Edward Duffy - Arlington MA, US

Assignee:

Egenera, Inc. - Marlborough MA

International Classification:

G06F 15/16

US Classification:

709245, 709238

Abstract:

A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

US Patent:

7231430, Jun 12, 2007

Filed:

Jan 4, 2002

Appl. No.:

10/038353

Inventors:

Vern Brownell - Chatham MA, US
Pete Manca - Sterling MA, US
Ben Sprachman - Hopkinton MA, US
Paul Curtis - Sudbury MA, US
Ewan Milne - Stow MA, US
Max Smith - Natick MA, US
Alan Greenspan - Northboro MA, US
Scott Geng - Westboro MA, US
Dan Busby - Sterling MA, US
Edward Duffy - Arlington MA, US
Peter Schulter - Hampstead NH, US

Assignee:

Egenera, Inc. - Marlboro MA

International Classification:

G06F 15/16
G06F 15/173
G06F 15/167
H04L 12/56

US Classification:

709218, 709212, 709205, 709244, 37039553

Abstract:

A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

US Patent:

7305581, Dec 4, 2007

Filed:

Oct 13, 2005

Appl. No.:

11/250154

Inventors:

Scott Geng - Westboro MA, US
Pete Manca - Sterling MA, US
Paul Curtis - Sudbury MA, US
Ewan Milne - Stow MA, US
Max Smith - Natick MA, US
Alan Greenspan - Northboro MA, US
Edward Duffy - Arlington MA, US
Peter Schulter - Hampstead NH, US

Assignee:

Egenera, Inc. - Marlborough MA

International Classification:

G06F 11/00

US Classification:

714 11

Abstract:

A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor. The virtual storage space and defined correspondence of the failed processor is assigned to the processor that replaces the failed processor.

US Patent:

20020156613, Oct 24, 2002

Filed:

Jan 4, 2002

Appl. No.:

10/038355

Inventors:

Scott Geng - Westboro MA, US
Pete Manca - Sterling MA, US
Paul Curtis - Sudbury MA, US
Ewan Milne - Stow MA, US
Max Smith - Natick MA, US
Alan Greenspan - Northboro MA, US
Edward Duffy - Arlington MA, US
Peter Schulter - Hampstead NH, US

International Classification:

G06F009/455

US Classification:

703/023000

Abstract:

A platform for and method of computer processing to support processor failover are disclosed. A plurality of computer processors are connected to an internal communication network. A virtual local area communication network over the internal network is defined and established. Each computer processor in the virtual local area communication network has a corresponding virtual MAC address and the virtual local area network provides communication among a set of computer processors but excludes the processors from the plurality not in the defined set. A virtual storage space is defined and established with a defined correspondence to the address space of the storage network. In response to a failure by a computer processor, a computer processor from the plurality is allocated to replace the failed processor. The MAC address of the failed processor is assigned to the processor that replaces the failed processor. The virtual storage space and defined correspondence of the failed processor is assigned to the processor that replaces the failed processor. The virtual local area network is reestablished to include the processor that replaces the failed processor and to exclude the failed processor.

US Patent:

20030130832, Jul 10, 2003

Filed:

Jan 4, 2002

Appl. No.:

10/037191

Inventors:

Peter Schulter - Hampstead NH, US
Scott Geng - Westboro MA, US
Pete Manca - Sterling MA, US
Paul Curtis - Sudbury MA, US
Ewan Milne - Stow MA, US
Max Smith - Natick MA, US
Alan Greenspan - Northboro MA, US
Edward Duffy - Arlington MA, US

International Classification:

G06F009/455

US Classification:

703/023000

Abstract:

A virtual networking system and method are disclosed. Switched Ethernet local area network semantics are provided over an underlying point to point mesh. Computer processor nodes may directly communicate via virtual interfaces over a switch fabric or they may communicate via an ethernet switch emulation. Address resolution protocol logic helps associate IP addresses with virtual interfaces while allowing computer processors to reply to ARP requests with virtual MAC addresses.

US Patent:

20070233809, Oct 4, 2007

Filed:

Jun 6, 2007

Appl. No.:

11/759076

Inventors:

Vern BROWNELL - Chatham MA, US
Peter MANCA - Sterling MA, US
Ben SPRACHMAN - Hopkinton MA, US
Paul CURTIS - Sudbury MA, US
Ewan MILNE - Stow MA, US
Max SMITH - Natick MA, US
Alan GREENSPAN - Northborough MA, US
Scott GENG - Westboro MA, US
Dan BUSBY - Sterling MA, US
Edward DUFFY - Arlington MA, US
Peter SCHULTER - Hampstead NH, US

International Classification:

G06F 15/16

US Classification:

709218000

Abstract:

A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.

US Patent:

20070233810, Oct 4, 2007

Filed:

Jun 6, 2007

Appl. No.:

11/759077

Inventors:

Vern BROWNELL - Chatham MA, US
Pete MANCA - Sterling MA, US
Ben SPRACHMAN - Hopkinton MA, US
Paul CURTIS - Sudbury MA, US
Ewan MILNE - Stow MA, US
Max SMITH - Natick MA, US
Alan GREENSPAN - Northboro MA, US
Scott GENG - Westboro MA, US
Dan BUSBY - Sterling MA, US
Edward DUFFY - Arlington MA, US
Peter SCHULTER - Hampstead NH, US

International Classification:

G06F 15/16

US Classification:

709218000

Abstract:

A platform and method of deploying virtual processing areas networks are described. A plurality of computer processors are connected to an internal communication network. At least one control node is in communication with an external communication network and an external storage network has an external storage address space. The at least one control node is connected to the internal network and thereby is in communication with the plurality of computer processors. Configuration logic defines and establishes a virtual processing area network having a corresponding set of computer processors from the plurality of processors, a virtual local area communication network providing communication among the set of computer processors, and a virtual storage space with a defined correspondence to the address space of the storage network.