Fan Chu from 12715 Peregrine Way, Colorado Springs, CO 80908, age 64, Phone: 7192872934

Vehicle Records

Fan Chu
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Address:

12715 Peregrine Way, Colorado Springs, CO 80908
VIN:

JM3TB3DV5C0356468
Make:

MAZDA
Model:

CX-9
Year:

2012

Resumes

Senior Director, Technology Development Engineering

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Location:

Colorado Springs, CO

Industry:

Semiconductors

Work:

Ramtron May 2011 - Nov 2012
Chief Technologist
Cypress Semiconductor Corporation May 2011 - Nov 2012
Senior Director, Technology Development Engineering
Ramtron May 2006 - May 2011
Principal Scientist

Education:

Xianjiaotong University 1984 - 1987
Master of Science, Masters, Engineering Xianjiaotong University 1978 - 1982
Bachelors, Bachelor of Science, Engineering

Skills:

Semiconductor Industry
Ic
Soc
Electronics
Asic
Cmos
Mixed Signal
Analog
Engineering Management
Embedded Systems
Cross Functional Team Leadership
Analog Circuit Design
Verilog

Us Patents

Method For Manufacturing A Ferroelectric Memory Cell Including Co-Annealing
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US Patent:

6376259, Apr 23, 2002
Filed:

Mar 21, 2001
Appl. No.:

09/816425
Inventors:

Fan Chu - Colorado Springs CO
Glen Fox - Colorado Springs CO
Assignee:

Ramtron International Corporation - Colorado Springs CO
International Classification:

H01L 2100
US Classification:

438 3
Abstract:

A method for manufacturing a ferroelectric memory cell includes the steps of forming a bottom electrode layer on a substrate, forming a ferroelectric thin film layer on the bottom electrode layer, forming a top electrode on the ferroelectric thin film layer, forming an encapsulating layer on the top electrode, forming a contact hole through the encapsulating layer, and co-annealing the ferroelectric thin film layer and the top electrode after forming the contact hole.

Ferroelectric Semiconductor Memory Device And A Fabrication Process Thereof
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US Patent:

6617626, Sep 9, 2003
Filed:

Feb 28, 2001
Appl. No.:

09/797430
Inventors:

Soichiro Ozawa - Kawasaki, JP
Shan Sun - Colorado Springs CO
Hideyuki Noshiro - Kawasaki, JP
George Hickert - Colorado Springs CO
Katsuyoshi Matsuura - Kawasaki, JP
Fan Chu - Black Forest CO
Takeyasu Saito - Kawasaki, JP
Assignee:

Fujitsu Limited - Kawasaki
International Classification:

H01L 2976
US Classification:

257295, 257296
Abstract:

A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO , wherein the PZT film includes pinholes, with a pinhole density of about 17/m or less.

Ferroelectric Thin Film Capacitors Having Multi-Layered Crystallographic Textures
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US Patent:

6627930, Sep 30, 2003
Filed:

Mar 14, 2000
Appl. No.:

09/525974
Inventors:

Glen Fox - Colorado Springs CO
Fan Chu - Colorado Springs CO
Brian Eastep - Colorado Springs CO
Shan Sun - Colorado Springs CO
Assignee:

Fujitsu Limited - Kawasaki
International Classification:

H01L 27108
US Classification:

257295, 257306
Abstract:

A ferroelectric thin film capacitor and a method for producing the same wherein the capacitor dielectric includes multi-layered crystallographic textures. An integrated circuit device, such as a non-volatile memory device, includes at least one capacitor having a top and bottom electrode thereof and a ferroelectric dielectric layer therebetween. The ferroelectric dielectric layer comprises a first ferroelectric layer having a first crystallographic texture forming a main body of the dielectric layer and a second ferroelectric layer having a second differing crystallographic texture forming an interface layer between the main body and one of the top and bottom electrodes.

Ferroelectric Semiconductor Memory Device And A Fabrication Process Thereof
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US Patent:

6777287, Aug 17, 2004
Filed:

May 23, 2003
Appl. No.:

10/445124
Inventors:

Soichiro Ozawa - Kawasaki, JP
Shan Sun - Colorado Springs CO
Hideyuki Noshiro - Kawasaki, JP
George Hickert - Colorado Springs CO
Katsuyoshi Matsuura - Kawasaki, JP
Fan Chu - Black Forest CO
Takeyasu Saito - Kawasaki, JP
Assignee:

Fujitsu Limited - Kawasaki
International Classification:

H01L 218242
US Classification:

438240, 438 3, 438250, 438393
Abstract:

A ferroelectric random access memory has a ferroelectric capacitor formed of a stacking of a lower electrode, a PZT film and an upper electrode of SrRuO , wherein the PZT film includes pinholes, with a pinhole density of about 17 m or less.

Process For Producing High Quality Pzt Films For Ferroelectric Memory Integrated Circuits
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US Patent:

6887716, May 3, 2005
Filed:

Dec 20, 2000
Appl. No.:

09/742204
Inventors:

Glen Fox - Colorado Springs CO, US
Fan Chu - Colorado Springs CO, US
Brian Eastep - Colorado Springs CO, US
Tomohiro Takamatsu - Iwate, JP
Yoshimasa Horii - Iwate, JP
Ko Nakamura - Kanagawa, JP
Assignee:

Fujitsu Limited - Kawasaki
International Classification:

H01L021/00
US Classification:

438 3, 438239, 438240, 438957
Abstract:

A method for fabrication of ferroelectric capacitor elements of an integrated circuit includes steps of deposition of an electrically conductive bottom electrode layer, preferably made of a noble metal. The bottom electrode is covered with a layer of ferroelectric dielectric material. The ferroelectric dielectric is annealed with a first anneal prior to depositing a second electrode layer comprising a noble metal oxide. Deposition of the electrically conductive top electrode layer is followed by annealing the layer of ferroelectric dielectric material and the top electrode layer with a second anneal. The first and the second anneal are performed by rapid thermal annealing.

Semiconductor Device Having A Ferroelectric Capacitor And A Fabrication Process Thereof
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US Patent:

6964873, Nov 15, 2005
Filed:

Apr 17, 2000
Appl. No.:

09/551233
Inventors:

Katsuyoshi Matsuura - Kawasaki, JP
Mari Tani - Kawasaki, JP
Yoshimasa Horii - Kawasaki, JP
Fan Chu - Colorado Springs CO, US
Glen R. Fox - Colorado Springs CO, US
Brian Eastep - Colorado Springs CO, US
Assignee:

Fujitsu Limited - Kawasaki
International Classification:

H01L021/00
H01L021/8242
US Classification:

438 3, 438240, 438253, 438381
Abstract:

A method of fabricating a semiconductor device having a ferroelectric capacitor includes the steps of forming a lower electrode layer of the ferroelectric capacitor on an insulation film covering an active device element, forming a ferroelectric film on the lower electrode layer as a capacitor insulation film, crystallizing the ferroelectric film by applying a thermal annealing process in an atmosphere containing a non-oxidizing gas and an oxidizing gas, and forming an upper electrode layer on the ferroelectric film.

Circuit For Generating A Centered Reference Voltage For A 1T/1C Ferroelectric Memory
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US Patent:

7116572, Oct 3, 2006
Filed:

Nov 9, 2004
Appl. No.:

10/984065
Inventors:

Shan Sun - Colorado Springs CO, US
Xiao-Hong Du - Colorado Springs CO, US
Fan Chu - Colorado Springs CO, US
Bob Sommervold - Colorado Springs CO, US
Assignee:

Ramtron International Corporation - Colorado Springs CO
International Classification:

G11C 11/22
US Classification:

365145, 365149, 438 3
Abstract:

A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.

Circuit For Generating A Centered Reference Voltage For A 1T/1C Ferroelectric Memory
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US Patent:

7313010, Dec 25, 2007
Filed:

Jun 23, 2006
Appl. No.:

11/426165
Inventors:

Shan Sun - Colorado Springs CO, US
Xiao-Hong Du - Colorado Springs CO, US
Fan Chu - Colorado Springs CO, US
Bob Sommervold - Colorado Springs CO, US
Assignee:

Ramtron International Corporation - Colorado Springs CO
International Classification:

G11C 11/22
US Classification:

365145, 365149, 438 3
Abstract:

A ferroelectric reference circuit generates a reference voltage proportional to (P+U)/2 and is automatically centered between the bit line voltages corresponding to the P term and the U term across wide temperature and voltage ranges. To avoid fatiguing the reference ferroelectric capacitors generating (P+U)/2, the reference voltage is refreshed once every millisecond. To eliminate the variation of the reference voltage due to the leakage in the ferroelectric capacitors during this period of time, the reference voltage generated from the reference ferroelectric capacitors is digitized when it is refreshed. The digital value is fixed and converted to an analog value which is then fed into sense amplifiers for resolving the data states. The reference voltage is automatically at the center of the switching (P) and non-switching (U) signals and therefore the signal margin is maximized.