Fan Ben Yeung from Irvine, CA, age 50

Semiconductor Chip Bump Connection Apparatus And Method
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US Patent:

7670939, Mar 2, 2010
Filed:

May 12, 2008
Appl. No.:

12/119174
Inventors:

Roden R. Topacio - Markham, CA
Vincent Chan - Richmond Hill, CA
Fan Yeung - Irvine CA, US
Assignee:

ATI Technologies ULC - Markham, Ontario
International Classification:

H01L 21/44
US Classification:

438612, 438706, 257E21006, 257E21079, 257E21499, 257E21509
Abstract:

Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.

Semiconductor Chip Bump Connection Apparatus And Method
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US Patent:

8378471, Feb 19, 2013
Filed:

Jan 22, 2010
Appl. No.:

12/692239
Inventors:

Roden R. Topacio - Markham, CA
Vincent Chan - Richmond Hill, CA
Fan Yeung - Irvine CA, US
Assignee:

ATI Technologies ULC - Markham, Ontario
International Classification:

H01L 23/02
US Classification:

257678, 257779, 257E21006, 257E21079, 257E21499, 257E21509
Abstract:

Various semiconductor chip packages and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a solder bump to a side of a semiconductor chip and bringing the solder bump into contact with a conductor pad coupled to a substrate and positioned in an opening of a solder mask on the substrate. The conductor pad has a first lateral dimension and the opening has a second lateral dimension that is larger than the first lateral dimension. A metallurgical bond is established between the solder bump and the conductor pad.

I/O Connection Scheme For Qfn Leadframe And Package Structures
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US Patent:

20090243054, Oct 1, 2009
Filed:

Mar 31, 2008
Appl. No.:

12/059526
Inventors:

Fan Yeung - Irvine CA, US
Sam Ziqun Zhao - Irvine CA, US
Nir Matalon - Sunnyvale CA, US
Victor Fong - Cupertino CA, US
Assignee:

BROADCOM CORPORATION - Irvine CA
International Classification:

H01L 23/495
H05K 7/18
H01L 21/56
US Classification:

257666, 361813, 438122, 257E23031, 257E21502
Abstract:

Methods, systems, and apparatuses for integrated circuit packages and lead frames are provided. A quad flat no-lead (QFN) package includes a plurality of peripherally positioned pins, a die-attach paddle, an integrated circuit die, and an encapsulating material. The die-attach paddle is positioned within a periphery formed by the pins. The die is attached to the die-attach paddle. The encapsulating material encapsulates the die on the die-attach paddle, encapsulates bond wires connected between the die and the pins, and fills a space between the pins and the die-attach paddle. One or more of the pins are extended. An extended pin may be elongated, L shaped, T shaped, or “wishbone” shaped. The extended pin(s) enable wire bonding of additional ground, power, and I/O (input/output) pads of the die in a manner that does not significantly increase QFN package cost.

Method And Apparatuses For Integrated Circuit Substrate Manufacture
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US Patent:

20130001791, Jan 3, 2013
Filed:

Jun 28, 2011
Appl. No.:

13/170820
Inventors:

Fan YEUNG - Irvine CA, US
Edward LAW - Ladera Ranch CA, US
Assignee:

Broadcom Corporation - Irvine CA
International Classification:

H01L 23/52
H01L 21/50
US Classification:

257773, 438121, 257E21499, 257E23141
Abstract:

Embodiments described herein provide a method of manufacturing integrated circuit (IC) devices. The method includes coupling a first surface of a first intermediate substrate to a first surface of a second intermediate substrate, forming a first plurality of patterned metal layers on a second surface of the first intermediate substrate to form a first substrate and a second plurality of patterned metal layers on a second surface of the second intermediate substrate to form a second substrate, and separating the first and second substrates. Each of the first substrate and the second substrate is configured to facilitate electrical interconnection between a respective IC die and a respective printed circuit board (PCB).