Farhad Iryami

US Patent:

6880070, Apr 12, 2005

Filed:

Oct 12, 2001

Appl. No.:

09/976765

Inventors:

Paul R. Gentieu - Sunnyvale CA, US
Tom Acquistapace - Martinez CA, US
Farhad Iryami - Millbrae CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

G08F013/00

US Classification:

712228

Abstract:

A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

US Patent:

6975395, Dec 13, 2005

Filed:

Dec 11, 2002

Appl. No.:

10/318286

Inventors:

Paul Gentieu - Sunnyvale CA, US
Craig Howard - Belmont CA, US
Farhad Iryami - Millbrae CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

G01J003/28
H04B010/08

US Classification:

356326, 356402, 398 25, 398 26, 398 31

Abstract:

A handheld optical unit is disclosed to measure optical characteristics of an optical input. A personal digital assistant is mounted to a housing to serve as a host computer for an optical spectrum analyzer disposed within the housing.

US Patent:

7032139, Apr 18, 2006

Filed:

Jun 24, 2002

Appl. No.:

10/179760

Inventors:

Farhad Iryami - Millbrae CA, US
Paul Gentieu - Sunnyvale CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

H03M 13/01

US Classification:

714704, 398 16, 398 27, 714715, 714716

Abstract:

The present invention is a bit error rate tester that may operate on network paths having devices that add or drop idles within a transmitted bit sequence. In particular, the bit sequence determines whether a received bit sequence is synchronized. If the received sequence is not synchronized or if a certain event/threshold is reached, then the bit error rate tester re-synchronizes the sequence prior to analysis. Also, the bit error rate detector is able to operate on high-speed networks and provide bit granularity measurements.

US Patent:

7360065, Apr 15, 2008

Filed:

Apr 11, 2005

Appl. No.:

11/102977

Inventors:

Paul R. Gentieu - Sunnyvale CA, US
Tom Acquistapace - Martinez CA, US
Farhad Iryami - Millbrae CA, US

Assignee:

Finisar Corporation - Sunnyvale CA

International Classification:

G06F 3/00

US Classification:

712220

Abstract:

A synchronous network traffic processor that synchronously processes, analyzes and generates data for high-speed network protocols, on a wire-speed, word-by-word basis. The synchronous network processor is protocol independent and may be programmed to convert protocols on the fly. An embodiment of the synchronous network processor described has a low gate count and can be easily implemented using programmable logic. An appropriately programmed synchronous network traffic processor may replace modules traditionally implemented with hard-wired logic or ASIC.

US Patent:

62688081, Jul 31, 2001

Filed:

Jun 8, 1999

Appl. No.:

9/327997

Inventors:

Farhad Iryami - Millbrae CA
Mark Farley - Napa CA

Assignee:

Finisar Corporation - Mountain View CA

International Classification:

H03M 700

US Classification:

341 51

Abstract:

A data modifier including a trigger subsystem and a modification subsystem. The trigger subsystem generates a trigger signal when it detects the presence of a user predefined pattern in an input data stream. The modification subsystem responds to the trigger signal by altering user specified portions of a first input datum of the input data stream to create a corresponding output datum having a fixed, real-time delay with respect to the first input datum.