Feng Hsueh Lin

US Patent:

6418537, Jul 9, 2002

Filed:

Jul 8, 1999

Appl. No.:

09/350414

Inventors:

Kewei Yang - San Jose CA
Feng Cheng Lin - Union City CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 104

US Classification:

713400, 713503, 710 60

Abstract:

In a preferred embodiment, the invention uses an 8-to-1 data serialization circuit in the transmitter to convert 80-bit parallel 200 MHz data to 10-bit parallel 1. 6 Mb/s date. On the receiver side, data are captured using a forwarded clock and de-serialized. A single global DLL generates 16 master phases without reference to the word boundaries of data being transmitted. These 16 unreferenced phases are input to a phase rotator that, via a series of calibration steps, maps the unreferenced phases into named phases, and in doing so references the phases to the word boundary of the data being transmitted over the slowest data line of the parallel channel. The named phases are then input to a data interpolator in each receiver, which generates 16 local phases. The 16 local phases correspond to the data-bit centers and data-bit edges for each of the 8 bits transferred per major channel clock period. In a bit-centering calibration step, a training pattern is evaluated by each receiver and each data interpolator dynamically adjusts a delay applied to the 16 local phases to establish the local center-data phases in the center of the bits received by the corresponding receiver.

US Patent:

6469988, Oct 22, 2002

Filed:

Jul 8, 1999

Appl. No.:

09/349832

Inventors:

Kewei Yang - San Jose CA
Feng Cheng Lin - Union City CA
Yang Jing Ke - Union City CA

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

H04B 320

US Classification:

370289, 370296, 375220, 375346

Abstract:

Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1. 6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices.

US Patent:

7028134, Apr 11, 2006

Filed:

Dec 28, 2000

Appl. No.:

09/750629

Inventors:

Yuanlong Wang - San Jose CA, US
Kewei Yang - San Jose CA, US
Daniel Fu - Sunnyvale CA, US
Feng Cheng Lin - Union City CA, US

Assignee:

Conexant Systems, Inc. - Newport Beach CA

International Classification:

G06F 13/00

US Classification:

710317, 710316, 370360

Abstract:

Communication circuitry is comprised of processing circuitry, parallel channels, and crossbar integrated circuits. The processing circuitry exchanges the communications between communication links and the parallel channels. The parallel channels transfer the communications in parallel with a clock signal. The crossbar integrated circuits receive the communications and the clock signal over the parallel channels, switch the communications based on the clock signal, and transfer the switched communications to the parallel channels.