Feng Baohua Pan

US Patent:

6359824, Mar 19, 2002

Filed:

Jun 9, 2000

Appl. No.:

09/592474

Inventors:

Colin S. Bill - Cupertino CA
Jonathan Shi-Chang Su - Mountain View CA
Feng Pan - Richmond CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 800

US Classification:

365226, 365201

Abstract:

The present invention discloses a method and system for activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in a memory device. A plurality of wordline voltage supply circuits supply voltage for the wordlines. During operation, when the memory device is placed in a test mode requiring application of the predetermined high voltage to the wordlines, the wordline decoder circuits are activated. In addition, a first predetermined voltage that is approximately zero volts is supplied by the wordline voltage supply circuits to the wordline decoder circuits for a first predetermined amount of time. Once the wordline decoder circuits decode the respective wordlines, the first predetermined voltage is transferred to the respective wordlines. The wordline voltage supply circuits then supply a second predetermined voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a second predetermined amount of time. Finally, the wordline voltage supply circuits supply a predetermined high voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a third predetermined amount of time.

US Patent:

6370065, Apr 9, 2002

Filed:

Sep 22, 2000

Appl. No.:

09/667347

Inventors:

Feng Pan - Richmond CA
Colin Bill - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518511, 36518533

Abstract:

A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of memory cells simultaneously. In order to minimize the time required to complete the APDEV and APDE functions, latches store for the address lines of the sector column positions. The APDEV function, therefore, can be performed serially on each of the sectors in the multiple sector group instead of all the sectors in the group simultaneously, thereby decreasing the amount of time required for the APDEV and APDE functions during the fast erase mode.

US Patent:

6385093, May 7, 2002

Filed:

Mar 30, 2001

Appl. No.:

09/822995

Inventors:

Kazuhiro Kurihara - Sunnyvale CA
Feng Pan - Richmond CA
Weng Fook Lee - Santa Clara CA
Ravi Sunkavalli - Milpitas CA
Darlene Hamilton - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518529, 36518511, 36518519

Abstract:

A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

US Patent:

6587590, Jul 1, 2003

Filed:

Feb 22, 2000

Appl. No.:

09/402367

Inventors:

Feng Pan - Cupertino CA

Assignee:

The Trustees of the University of Pennsylvania - Philadelphia PA

International Classification:

G06K 936

US Classification:

382250, 708402

Abstract:

A method and system for computing 2-D DCT/IDCT which is easy to implement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8Ã8 DCT/IDCT is computed through four 4Ã4 matrix multiplication sub-blocks. Each sub-block is half the size of the original 8Ã8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.

US Patent:

6587982, Jul 1, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/654965

Inventors:

Weng F. Lee - Penang, MY
Colin S. Bill - Cupertino CA
Feng Pan - San Jose CA
Edward V. Bautista - Santa Clara CA
Azrul Halim - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G01R 3128

US Classification:

714733

Abstract:

There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.

US Patent:

6622274, Sep 16, 2003

Filed:

Sep 5, 2000

Appl. No.:

09/655335

Inventors:

Weng F. Lee - Penang, ML
Colin S. Bill - Cupertino CA
Feng Pan - San Jose CA
Edward V. Bautista - Santa Clara CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 2900

US Classification:

714733, 714718, 714734

Abstract:

There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I. C. chip area was realized in comparison to the implementation by a conventional state machine.

US Patent:

6661711, Dec 9, 2003

Filed:

Feb 6, 2002

Appl. No.:

10/068245

Inventors:

Feng Pan - San Jose CA
Tat-Kwan Edgar Yu - Cupertino CA

Assignee:

Sandisk Corporation - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

3651853, 36518529, 36518524

Abstract:

Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.

US Patent:

6696880, Feb 24, 2004

Filed:

Nov 9, 2001

Appl. No.:

10/014161

Inventors:

Feng Pan - San Jose CA
Khandker N. Quader - Sunnyvale CA

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

H03K 1716

US Classification:

327390, 327589, 326 88, 36523008

Abstract:

The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.