Feng Pan

age ~44

from Palo Alto, CA

Also known as:
  • Feng Fan
  • Pan Feng

Feng Pan Phones & Addresses

  • Palo Alto, CA
  • San Antonio, TX
  • San Jose, CA
  • Seattle, WA
  • Indianapolis, IN
  • Miami, FL
  • Newark, DE
  • Elmhurst, NY
  • 1721 Castlegate Dr, San Jose, CA 95132

Work

  • Position:
    Building and Grounds Cleaning and Maintenance Occupations

Education

  • Degree:
    Associate degree or higher

Resumes

Feng Pan Photo 1

Feng Pan

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Feng Pan Photo 2

Feng Pan

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Location:
United States
Name / Title
Company / Classification
Phones & Addresses
Feng Pan
Roxie International, LLC
Grocery Retail · Grocery Store · Business Services at Non-Commercial Site · Nonclassifiable Establishments
500 Kirkham St, San Francisco, CA 94122
1025 Geranio Dr, Alhambra, CA 91801

Us Patents

  • Activation Of Wordline Decoders To Transfer A High Voltage Supply

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  • US Patent:
    6359824, Mar 19, 2002
  • Filed:
    Jun 9, 2000
  • Appl. No.:
    09/592474
  • Inventors:
    Colin S. Bill - Cupertino CA
    Jonathan Shi-Chang Su - Mountain View CA
    Feng Pan - Richmond CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G11C 800
  • US Classification:
    365226, 365201
  • Abstract:
    The present invention discloses a method and system for activating a plurality of wordline decoder circuits to transfer a predetermined high voltage to a plurality of wordlines during a test mode in a memory device. A plurality of wordline voltage supply circuits supply voltage for the wordlines. During operation, when the memory device is placed in a test mode requiring application of the predetermined high voltage to the wordlines, the wordline decoder circuits are activated. In addition, a first predetermined voltage that is approximately zero volts is supplied by the wordline voltage supply circuits to the wordline decoder circuits for a first predetermined amount of time. Once the wordline decoder circuits decode the respective wordlines, the first predetermined voltage is transferred to the respective wordlines. The wordline voltage supply circuits then supply a second predetermined voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a second predetermined amount of time. Finally, the wordline voltage supply circuits supply a predetermined high voltage that is transferred to the respective wordlines by the still activated wordline decoder circuits for a third predetermined amount of time.
  • I/O Partitioning System And Methodology To Reduce Band-To-Band Tunneling Current During Erase

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  • US Patent:
    6385093, May 7, 2002
  • Filed:
    Mar 30, 2001
  • Appl. No.:
    09/822995
  • Inventors:
    Kazuhiro Kurihara - Sunnyvale CA
    Feng Pan - Richmond CA
    Weng Fook Lee - Santa Clara CA
    Ravi Sunkavalli - Milpitas CA
    Darlene Hamilton - San Jose CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
    Fujitsu Limited - Kanagawa
  • International Classification:
    G11C 1604
  • US Classification:
    36518529, 36518511, 36518519
  • Abstract:
    A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.
  • Method And System For Computing 8×8 Dct/Idct And A Vlsi Implementation

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  • US Patent:
    6587590, Jul 1, 2003
  • Filed:
    Feb 22, 2000
  • Appl. No.:
    09/402367
  • Inventors:
    Feng Pan - Cupertino CA
  • Assignee:
    The Trustees of the University of Pennsylvania - Philadelphia PA
  • International Classification:
    G06K 936
  • US Classification:
    382250, 708402
  • Abstract:
    A method and system for computing 2-D DCT/IDCT which is easy to implement with VLSI technology to achieve high throughput to meet the requirements of high definition video processing in real time is described. A direct 2-D matrix factorization approach is utilized to compute the 2-D DCT/IDCT. The 8Ã8 DCT/IDCT is computed through four 4Ã4 matrix multiplication sub-blocks. Each sub-block is half the size of the original 8Ã8 size and therefore requires a much lower number of multiplications. Additionally, each sub-block can be implemented independently with localized interconnection so that parallelism can be exploited and a much higher DCT/IDCT throughput can be achieved.
  • Method Of Micro-Architectural Implementation Of Interface Between Bist State Machine And Tester Interface To Enable Bist Cycling

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  • US Patent:
    6587982, Jul 1, 2003
  • Filed:
    Sep 5, 2000
  • Appl. No.:
    09/654965
  • Inventors:
    Weng F. Lee - Penang, MY
    Colin S. Bill - Cupertino CA
    Feng Pan - San Jose CA
    Edward V. Bautista - Santa Clara CA
    Azrul Halim - Santa Clara CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G01R 3128
  • US Classification:
    714733
  • Abstract:
    There is provided a tester interface circuit for use with a BIST state machine and a method for micro-architectural implementation of the same so as to enable cycling through a BIST test. The tester interface circuit includes a storage device, a logic decoder, a set/clear mechanism, and a polling logic device. The tester interface circuit is implemented with a minimum amount of chip area on a semiconductor IC.
  • Method Of Micro-Architectural Implementation On Bist Fronted State Machine Utilizing €˜Death Logic’ State Transition For Area Minimization

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  • US Patent:
    6622274, Sep 16, 2003
  • Filed:
    Sep 5, 2000
  • Appl. No.:
    09/655335
  • Inventors:
    Weng F. Lee - Penang, ML
    Colin S. Bill - Cupertino CA
    Feng Pan - San Jose CA
    Edward V. Bautista - Santa Clara CA
  • Assignee:
    Advanced Micro Devices, Inc. - Sunnyvale CA
  • International Classification:
    G11C 2900
  • US Classification:
    714733, 714718, 714734
  • Abstract:
    There is provided an improve BIST frontend state machine and a method for micro-architectural implementation of the same which is achieved with a minimal amount of test logic circuitry. The state frontend machine includes a state controller responsive to clock signals, control signals, and output register signals for generating output state signals based upon a fixed number of states utilizing death logic so as to sequence through one of a plurality of sets of tests until completed or failed. A substantial savings of approximately 40% in the I. C. chip area was realized in comparison to the implementation by a conventional state machine.
  • Implementation Of An Inhibit During Soft Programming To Tighten An Erase Voltage Distribution

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  • US Patent:
    6661711, Dec 9, 2003
  • Filed:
    Feb 6, 2002
  • Appl. No.:
    10/068245
  • Inventors:
    Feng Pan - San Jose CA
    Tat-Kwan Edgar Yu - Cupertino CA
  • Assignee:
    Sandisk Corporation - Sunnyvale CA
  • International Classification:
    G11C 1604
  • US Classification:
    3651853, 36518529, 36518524
  • Abstract:
    Methods and apparatus for tightening an erased bit threshold voltage distribution are disclosed. According to one aspect of the present invention, a method for processing erased bits associated with an erased bit distribution which includes an over-erased bit which has a first value that is less than a first threshold voltage value and a bit that has a second value that substantially exceeds a second threshold voltage value includes inhibiting the fast bit. The method also includes applying a soft program pulse to the erased bits such that inhibiting the fast bit substantially prevents the second value from changing and applying the soft program pulse to the over-erased bit substantially causes the first value to increase. In one embodiment, applying the soft program pulse to the over-erased bit substantially causes the first value to increase to a value that is greater than or equal to the first threshold voltage value.
  • High Voltage Switch Suitable For Non-Volatile Memories

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  • US Patent:
    6696880, Feb 24, 2004
  • Filed:
    Nov 9, 2001
  • Appl. No.:
    10/014161
  • Inventors:
    Feng Pan - San Jose CA
    Khandker N. Quader - Sunnyvale CA
  • Assignee:
    SanDisk Corporation - Sunnyvale CA
  • International Classification:
    H03K 1716
  • US Classification:
    327390, 327589, 326 88, 36523008
  • Abstract:
    The invention utilizes a boost-strap method to improve switch operation in a design that is particularly advantageous for supplying high voltages within a low voltage design. A native NMOS transistor, a PMOS transistor, and a capacitor are connected in series between the high voltage source and the output, where the gate of the native NMOS is connect to the output. In an initialization phase, the plate of the capacitor connected to the output is precharged by receiving the input signal while the other plate of the capacitor is held near ground. In a subsequent enable phase, the native NMOS and PMOS transistors are turned on and the high voltage is supplied to the output.
  • High Voltage Ripple Reduction

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  • US Patent:
    6734718, May 11, 2004
  • Filed:
    Dec 23, 2002
  • Appl. No.:
    10/328686
  • Inventors:
    Feng Pan - San Jose CA
  • Assignee:
    SanDisk Corporation - Sunnyvale CA
  • International Classification:
    G06F 110
  • US Classification:
    327536
  • Abstract:
    In a non-volatile memory, charge pumps are used to provide high voltages needed for programming memory cells that have floating gate structures. Charge pumps have a series of voltage multiplier stages in series to boost voltage. These charge pumps must rapidly charge a load to a high voltage and then maintain a voltage with a high degree of stability. Techniques for achieving both of these goals are presented. In one aspect, a charge pump has two operating states, one to charge a load rapidly and a second to maintain a voltage on a charged load with high stability. These states are achieved by changing the current output from a high current during charging to a low current to maintain the voltage. This is done by changing the capacitance used in the individual voltage multiplier stages. In another aspect, two different current levels are produced by changing the voltage used to charge the capacitors of the voltage multiplier stages.

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Feng Pan Photo 3

Feng Pan

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Feng Pan Photo 4

Feng Pan

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Feng Pan Photo 5

Pan Feng

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Feng Pan Photo 6

Feng Pan

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Feng Pan Photo 7

Feng Pan

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Feng Pan Photo 8

Feng Pan

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Feng Pan Photo 9

Yu Feng Pan

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Feng Pan Photo 10

Feng Pan

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Flickr

Googleplus

Feng Pan Photo 14

Feng Pan

Education:
Brooklyn College - Accounting
Feng Pan Photo 15

Feng Pan

Feng Pan Photo 16

Feng Pan

Education:
= Overrated
Feng Pan Photo 17

Feng Pan

Feng Pan Photo 18

Feng Pan

Feng Pan Photo 19

Feng Pan

Feng Pan Photo 20

Feng Pan

Feng Pan Photo 21

Feng Pan

Classmates

Feng Pan Photo 22

Washington University - B...

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Graduates:
Feng Pan (1996-2000),
Angela Trice (1983-1986),
Todd Waltermire (1992-1996),
Robert Linnemann (1982-1986)
Feng Pan Photo 23

University of Missouri - ...

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Graduates:
Feng Pan (2003-2005),
Tamara Wirth (1988-1992),
Mary Beth Jerry (2004-2008)

Youtube

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Pan Feng *DESTORYS* Hua Xiong!! #rotk #threekingdoms #huaxiong.

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Feng Shui Lo Pan Compasses

Feng Shui Lo Pan Compasses. Part of the series: Feng Shui Elements & D...

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House Feng Shui in Period 9 (Part 2) | Flying...

House Feng Shui in Period 9 (Part 2) | Flying Stars Period 8 | Feng Sh...

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KLF 59: Pan Jiayun vs Feng Zhiqiang HIGHLIGHT...

If you like our videos, give us a thumbs up and click subscribe to sta...

  • Duration:
    2m 34s

Heng Feng Pan Lipsticks Review..!! Awesome Co...

Assalamualaikum Everyone...so kese hen AP sb...?? Ajki meri video he m...

  • Duration:
    4m 35s

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