Feng Zhaohui C Pan

US Patent:

6370065, Apr 9, 2002

Filed:

Sep 22, 2000

Appl. No.:

09/667347

Inventors:

Feng Pan - Richmond CA
Colin Bill - Cupertino CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518511, 36518533

Abstract:

A method for serial sequencing the automatic disturb erase verify (APDEV) function during a multiple sector fast erase mode. The fast erase mode allows a memory device to erase several sectors of memory cells simultaneously. In order to minimize the time required to complete the APDEV and APDE functions, latches store for the address lines of the sector column positions. The APDEV function, therefore, can be performed serially on each of the sectors in the multiple sector group instead of all the sectors in the group simultaneously, thereby decreasing the amount of time required for the APDEV and APDE functions during the fast erase mode.

US Patent:

6385093, May 7, 2002

Filed:

Mar 30, 2001

Appl. No.:

09/822995

Inventors:

Kazuhiro Kurihara - Sunnyvale CA
Feng Pan - Richmond CA
Weng Fook Lee - Santa Clara CA
Ravi Sunkavalli - Milpitas CA
Darlene Hamilton - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

G11C 1604

US Classification:

36518529, 36518511, 36518519

Abstract:

A system is provided for reducing band-to-band tunneling current during Flash memory erase operations. The system includes a memory sector divided into (N) I/O subsectors, N being an integer, and a drain pump to generate power for associated erase operations within the N I/O subsectors. An erase sequencing subsystem generates N pulses to enable the erase operations within each of the N I/O subsectors in order to reduce band-to-band tunneling current provided by the drain pump.

US Patent:

6944068, Sep 13, 2005

Filed:

Mar 24, 2004

Appl. No.:

10/809571

Inventors:

Khandker N. Quader - Sunnyvale CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/06

US Classification:

36518922, 36518503, 36518512, 36518524

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

6967872, Nov 22, 2005

Filed:

Dec 18, 2001

Appl. No.:

10/025749

Inventors:

Khandker N. Quader - Sunnyvale CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Sunnyvale CA

International Classification:

G11C016/04

US Classification:

36518522, 36518502, 36518503

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

7057949, Jun 6, 2006

Filed:

Jan 16, 2002

Appl. No.:

10/050342

Inventors:

Feng Pan - Richmond CA, US
Weng Fook Lee - Penang, ML
Santosh K. Yachareni - Santa Clara CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 7/00

US Classification:

365203, 365218

Abstract:

Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.

US Patent:

7095654, Aug 22, 2006

Filed:

Sep 9, 2005

Appl. No.:

11/223709

Inventors:

Khandker N. Quader - Santa Clara CA, US
Khanh T. Nguyen - Sunnyvale CA, US
Feng Pan - San Jose CA, US
Long C. Pham - San Jose CA, US
Alexander K. Mak - Los Altos Hills CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 11/34

US Classification:

36518519, 36518518, 365196

Abstract:

A multi-level non-volatile memory cell programming/lockout method and system are provided. The programming/lockout method and system advantageously prevent memory cells that charge faster than other memory cells from being over-programmed.

US Patent:

7368979, May 6, 2008

Filed:

Sep 19, 2006

Appl. No.:

11/523875

Inventors:

Prashanti Govindu - Santa Clara CA, US
Feng Pan - Fremont CA, US
Man Mui - Santa Clara CA, US
Gyuwan Kwon - Cupertino CA, US
Trung Pham - Fremont CA, US
Chi-Ming Wang - Fremont CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G05F 1/10

US Classification:

327536

Abstract:

According to different embodiments of the present invention, various methods, devices and systems are described for managing power in charge pumps in a non-volatile memory system having a high voltage charge pump and associated regulator. A method includes the following operations, receiving an operation command corresponding to an operation, pumping up a charge pump output voltage to a desired output voltage, turning off the regulator and the charge pump when the output voltage is approximately the desired output voltage compensating for charge sharing by turning on the charge pump and setting a pump clock rate to a slow clock rate in order to avoid overshooting the desired output voltage by the charge pump while the operation is being carried out, and compensating for junction leakage by turning on the regulator and the charge pump until the charge pump output voltage is the desired output voltage.

US Patent:

7440342, Oct 21, 2008

Filed:

Dec 29, 2006

Appl. No.:

11/618522

Inventors:

Feng Pan - Fremont CA, US

Assignee:

SanDisk Corporation - Milpitas CA

International Classification:

G11C 5/14

US Classification:

36518909, 365226, 327538

Abstract:

Unified voltage generation techniques for efficiently generating a plurality of operational voltages for use within an electronic device, such as a memory system (e. g. , memory product) providing data storage, are disclosed. A voltage generation circuit can generate a regulated base output voltage. The voltage generation circuit can include one or more voltage output circuits that produce different operational voltages from the regulated base output voltage. According to one aspect of the invention, the voltage output circuits can be disabled when the different operational voltages are at their appropriate voltage potentials, thereby reducing power consumption by the voltage output circuits. The voltage generation circuit is therefore able to operate with improved power efficiency.