Feng Zhu

US Patent:

8082333, Dec 20, 2011

Filed:

Nov 10, 2008

Appl. No.:

12/267774

Inventors:

Dehua Huang - Los Altos CA, US
Premkumar Jonnala - Fremont CA, US
Nagarani Chandika - Cupertino CA, US
Kyle Gordon Haight - San Jose CA, US
Feng Zhu - San Jose CA, US
Dan Mihai Florea - Saratoga CA, US
Bimohit Bawa - Sunnyvale CA, US

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 15/177

US Classification:

709222, 709220

Abstract:

A DHCP proxy agent is provided to send on behalf of a static host a DHCP request so that an access layer security feature such as DHCP snooping/IPSG can be applied to the static host and/or in a mixed static IP and DHCP environment.

US Patent:

20130268726, Oct 10, 2013

Filed:

Dec 30, 2011

Appl. No.:

13/993596

Inventors:

Xin Guo - San Jose CA, US
Kiran Pangal - Fremont CA, US
Paul D. Ruby - Folsom CA, US
Feng Zhu - San Jose CA, US

International Classification:

G06F 12/02

US Classification:

711103

Abstract:

Host writes may be handled differently from background writes to non-volatile memory systems. As a result of using different write algorithms for host writes and backgrounds writes, maximum system lifetime and the maximum system performance may be improved in some embodiments.

US Patent:

20130339603, Dec 19, 2013

Filed:

Dec 23, 2011

Appl. No.:

13/997514

Inventors:

Feng Zhu - San Jose CA, US
Pranav Kalavade - San Jose CA, US
Iwen Chao - Sacramento CA, US

International Classification:

G06F 3/06

US Classification:

711114

Abstract:

Techniques and mechanisms for determining a sequence of accessed to a memory array. In an embodiment, a memory array includes multi-level cells and single-level cells interleaved with one another, where bits of the multi-level cells and single-level cells are variously allocated to different logical pages. In another embodiment, requests to access the memory array are ordered according to a sequence of page rounds to avoid an access event which includes a type of successive accessing of adjacent multi-level cells.

US Patent:

20190042112, Feb 7, 2019

Filed:

Mar 20, 2018

Appl. No.:

15/927042

Inventors:

- Santa Clara CA, US
Feng Zhu - San Jose CA, US
Xin Guo - San Jose CA, US
Simon D. Ramage - Vancouver BC, CA
Ning Wu - Folsom CA, US

International Classification:

G06F 3/06
G11C 16/34
G06F 11/30

Abstract:

Embodiments of the present disclosure may relate to a data storage controller that may include a non-volatile memory, and a processor coupled with the non-volatile memory to perform a scan of a plurality of non-volatile memory dies in a multi-die memory package to detect one or more defective non-volatile memory dies, where an individual non-volatile memory die of the plurality of non-volatile memory dies is defective if the individual non-volatile memory die has a number of bad blocks that exceeds a predefined threshold, and store one or more defective die indicators in a die topology in the non-volatile memory based at least in part on the scan, where the one or more defective die indicators correspond to the one or more defective non-volatile memory dies. Other embodiments may be described and/or claimed.

US Patent:

20170139626, May 18, 2017

Filed:

Jan 30, 2017

Appl. No.:

15/419563

Inventors:

- Santa Clara CA, US
Aliasgar Madraswala - Folsom CA, US
Pranav Kalavade - San Jose CA, US
Xin Guo - San Jose CA, US
David Pelster - Longmont CO, US
Myron Loewen - Loveland CO, US
Feng Zhu - San Jose CA, US
Brennan A. Watt - Boulder CO, US

International Classification:

G06F 3/06
G06F 12/0811

Abstract:

Methods, apparatus, systems and articles of manufacture to preserve data of a solid state drive during a power loss event are disclosed. An example method includes setting an alternate data cache (PDC) to a logical AND of a secondary data cache (SDC) and a primary data cache (PDC). The PDCis set to a logical AND of the PDCand a first result of a first sense operation. The PDCis set to a logical AND of the PDCand an inverse value of the PDC. The PDCis set to a logical AND of the SDC and the PDC. The PDCis set to a logical AND of the PDCand an inverse value of a second result of a second sense operation. The SDC is set to a logical AND of the SDC and the PDC. The SDC is set to a logical OR of the SDC or the PDC. The PDCis set to a logical AND of the PDCand a third result of a third sensing operation.

US Patent:

20170046073, Feb 16, 2017

Filed:

Aug 10, 2015

Appl. No.:

14/822793

Inventors:

- Santa Clara CA, US
Feng ZHU - San Jose CA, US
Eric L. HOFFMAN - Lafayette CO, US
Jing-Jing LI - Santa Clara CA, US
David J. PELSTER - Longmont CO, US

International Classification:

G06F 3/06
G11C 5/02
G06F 12/10

Abstract:

Provided are a method and apparatus for remapping logical to physical addresses for a non-volatile memory having dies. Bands extend through the dies and planes in the dies extending through the bands define addressable blocks. A first remapping of a logical-to-physical mapping is performed by remapping logical addresses of blocks in a first end of the bands that map to defective physical blocks to map to good physical blocks at a second end of the bands. After performing the first remapping, a second remapping of the logical-to-physical mapping is performed by remapping logical addresses in the second end of bands that map to defective blocks to map to good physical blocks in the first end of bands.

US Patent:

20160283143, Sep 29, 2016

Filed:

Mar 27, 2015

Appl. No.:

14/672080

Inventors:

- Santa Clara CA, US
Feng Zhu - San Jose CA, US
Yogesh B. Wakchaure - Folsom CA, US
David J. Pelster - Longmont CO, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/06
G11C 14/00
G06F 11/10

Abstract:

Methods and apparatus related to a rotated planar XOR scheme for Varied-Sector-Size (VSS) enablement in flat indirection systems are described. In one embodiment, non-volatile memory stores user data in a first set of plurality of planes across a plurality of dies and parity data corresponding to the user data in a second set of plurality of planes. The user data in the first set of the plurality of planes across the plurality of dies and the second set of the plurality of planes is rotated to match a mapping of the parity data. Other embodiments are also disclosed and claimed.

US Patent:

20160180958, Jun 23, 2016

Filed:

Dec 22, 2014

Appl. No.:

14/579971

Inventors:

- Santa Clara CA, US
IWEN CHAO - Sacramento CA, US
XIN GUO - San Jose CA, US
PRANAV KALAVADE - San Jose CA, US
KRISHNA K. PARAT - Palo Alto CA, US
FENG ZHU - San Jose CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 16/34
G11C 16/26
G11C 16/32
G11C 16/14

Abstract:

Apparatus, systems, and methods to implement dynamic memory management in nonvolatile memory devices are described. In one example, a controller comprises logic to monitor at least one performance parameter of a nonvolatile memory, determine when the at least one performance parameter passes a threshold which indicates a degradation in performance for the nonvolatile memory, and in response to the at least one performance parameter passing the threshold, to modify at least one operational attribute of the nonvolatile memory. Other examples are also disclosed and claimed.