Forrest L Pierson

US Patent:

20030048781, Mar 13, 2003

Filed:

Feb 15, 2002

Appl. No.:

10/078175

Inventors:

Forrest Pierson - Dallas TX, US

Assignee:

WorldCom, INC. - Clinton MS

International Classification:

H04L012/56

US Classification:

370/389000

Abstract:

A system and method for moving voice telephone calls through a data network. More particularly, the system and method are directed to the efficient operation of using identification numbers to route data packets through a communications node without reformatting individual data packets to the native protocol of that communications node. The exception is when the data packet will be more efficiently handled within the overall communications network by routing different pieces of that data packet to different outgoing port cards in a particular communications node, then the data packet will be reformatted, if necessary, to the native protocol of that communications node. The system and method allow the outgoing port card to convert the data packet into the correct format for transmission to either the destination (customer) or the next communications node. Together port cards and data switches form nodes. The port card receives and transmits out signals through respective ports connected to links between nodes.

US Patent:

20030171039, Sep 11, 2003

Filed:

Mar 5, 2002

Appl. No.:

10/087983

Inventors:

Forrest Pierson - Dallas TX, US

International Classification:

H01R009/22

US Classification:

439/709000

Abstract:

An electrical box is provided for receiving an electrical unit. A low voltage section is configured to provide a low voltage connection, wherein a barrier isolates the low voltage connection. A high voltage section is separated from the low voltage section via the barrier to provide a high voltage connection. The high voltage section includes a plurality of bus bars, and a plurality of displacement connectors that are coupled to the plurality of bus bars and are configured redundantly to accept wires.

US Patent:

20040213227, Oct 28, 2004

Filed:

Jul 24, 2003

Appl. No.:

10/627390

Inventors:

Forrest Pierson - Dallas TX, US

Assignee:

WorldCom, INC. - Clinton MS

International Classification:

H04L012/56

US Classification:

370/389000

Abstract:

A method and system for improving the passage of silent or unused status of DsO channel to a data switch with a DsO switching capacity. The method allows the DsO channel source to be the only equipment that must engage a digital signal processor to remove silent and unused DsO channels from a DsO channel carrying data packet. The method provides for the DsO channel source, the intermediate nodes (data switches with DsO switching matrixes included) and DsO channel destination to recognize a simple and efficient means of passing suppression status of a DsO channel through the entire network.

US Patent:

62721283, Aug 7, 2001

Filed:

Jun 16, 1998

Appl. No.:

9/099671

Inventors:

Forrest L. Pierson - Dallas TX

Assignee:

MCI Communications Corporation - Washington DC

International Classification:

H04L 1266
H04L 1256

US Classification:

370352

Abstract:

A method and system of emulating a T1 link over an ATM network. A T1 line carrying a stream of T1 frames is terminated at a first ATM Data Terminating Equipment (DTE). T1 frames are loaded into ATM cells and sent over an ATM network to a second ATM DTE. The T1 frames are unloaded at the second ATM DTE, and sent to a switch matrix to be de-multiplexed. In one example of T1 emulation, two T1 payloads are inserted in each ATM cell payload. The corresponding T1 frame bits replace the two least significant bits in the VCI field of the ATM cell header. For quasi-fractional T1 emulation, three or four quasi-fractional T1 payloads can be carried in the ATM cell payload. For fractional T1 emulation, multiple fractional T1 payloads are carried in a fractional payload field, and a frame bit field is created in the ATM cell payload to carry the T1 frame bits. The use of a T1 framer at the second DTE is avoided by insuring the T1 frame bit positions are constant over successive ATM cells.

US Patent:

61953466, Feb 27, 2001

Filed:

Jun 16, 1998

Appl. No.:

9/097996

Inventors:

Forrest L. Pierson - Dallas TX

Assignee:

MCI Communications Corporation - Washington DC

International Classification:

H04L 1266
H04L 1256

US Classification:

370352

Abstract:

A method and system for processing a High level Data Link Control (HDLC) message despite the occurrence of a frame slip event in an Asynchronous Transfer Mode (ATM) receiver avoiding re-transmission of an HDLC message when a frame slip event occurs during reception of an HDLC message. In one embodiment, an ATM receiver receives an ATM cell, where the ATM cell carries one or more T1 payloads. Each T1 payload contains a plurality of timeslots, including an HDLC timeslot. The HDLC timeslot is read for each T1 payload prior to unloading each T1 payload from the ATM cell. The plurality of timeslots within each T1 payload are sent to a switch matrix, where the timeslots are de-multiplexed. The HDLC message is carried in the HDLC timeslot over a plurality of ATM cells and the HDLC message is processed despite the occurrence of a frame slip event.

US Patent:

20210373891, Dec 2, 2021

Filed:

Aug 13, 2021

Appl. No.:

17/402117

Inventors:

Forrest L. Pierson - Dallas TX, US

International Classification:

G06F 9/30
G06F 9/34
G06F 12/0875
G06F 12/0891
G06F 21/52

Abstract:

A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

US Patent:

20200183691, Jun 11, 2020

Filed:

Feb 17, 2020

Appl. No.:

16/792432

Inventors:

Forrest L. Pierson - Dallas TX, US

International Classification:

G06F 9/30
G06F 12/0891
G06F 12/0875
G06F 9/34
G06F 21/52

Abstract:

A method for changing a processor instruction randomly, covertly, and uniquely, so that the reverse process can restore it faithfully to its original form, making it virtually impossible for a malicious user to know how the bits are changed, preventing them from using a buffer overflow attack to write code with the same processor instruction changes into said processor's memory with the goal of taking control of the processor. When the changes are reversed prior to the instruction being executed, reverting the instruction back to its original value, malicious code placed in memory will be randomly altered so that when it is executed by the processor it produces chaotic, random behavior that will not allow control of the processor to be compromised, eventually producing a processing error that will cause the processor to either shut down the software process where the code exists to reload, or reset.

US Patent:

20190158430, May 23, 2019

Filed:

Jan 29, 2019

Appl. No.:

16/261279

Inventors:

- Dallas TX, US
Forrest Lawrence Pierson - Dallas TX, US

International Classification:

H04L 12/931
H04L 29/06
H04L 12/933
H04W 28/14

Abstract:

A data switch for a packet data switch includes switching nodes connected to each other in an interconnecting matrix, providing a multiplicity of data paths between an incoming data or telecom port and an outgoing data or telecom port of the data switch. The interconnecting switching nodes can achieve high capacity data switching by providing a partial switching solution at each node, distributing the switching load. A switching protocol for interconnecting switching nodes allows data packets to be selectively passed from any incoming port on an interconnecting switch node to any interconnecting switching node or outgoing port connected to it. In at least one example, the switching protocol has mechanisms in it to provide for the duplicating of the contents of the data packet and pass them to multiple interconnecting switching nodes or outgoing ports.