Francisco Jesus Leon

US Patent:

6730988, May 4, 2004

Filed:

Jan 8, 2003

Appl. No.:

10/338435

Inventors:

Francisco A. Leon - Palo Alto CA
Everett X. Wang - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2906

US Classification:

257618, 216 85, 385 45

Abstract:

Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.

US Patent:

6818559, Nov 16, 2004

Filed:

Mar 21, 2001

Appl. No.:

09/814424

Inventors:

Francisco A. Leon - Palo Alto CA
Everett X. Wang - San Jose CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21311

US Classification:

438700, 438701, 438689, 438 25, 438 26, 216 24, 216 11

Abstract:

Substantially sharp corners for optical waveguides in integrated optical devices, photonic crystal devices, or for micro-devices, can be fabricated. Non-sharp corners such as rounded corners, are first formed using lithographic patterning and vertical etching. Next, isotropic etching is used to sharpen the rounded corners. A monitor can be used to determine if the rounded corners have been sufficiently sharpened by the isotropic etching.

US Patent:

7001788, Feb 21, 2006

Filed:

May 28, 2004

Appl. No.:

10/858524

Inventors:

Francisco A. Leon - Palo Alto CA, US
Lawrence C. West - San Jose CA, US
Gregory L. Wojcik - Ben Lomond CA, US
Yuichi Wada - Tomisato, JP

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438 31

Abstract:

A method of fabricating a waveguide mirror that involves etching a trench in a silicon substrate; depositing a film (e. g. silicon dioxide) over the surface of the silicon substrate and into the trench; ion etching the film to remove at least some of the deposited silicon dioxide and to leave a facet of film in inside corners of the trench; depositing a layer of SiGe over the substrate to fill up the trench; and planarizing the deposited SiGe to remove the SiGe from above the level of the trench.

US Patent:

7075165, Jul 11, 2006

Filed:

May 28, 2004

Appl. No.:

10/856750

Inventors:

Francisco A. Leon - Palo Alto CA, US
Lawrence C. West - San Jose CA, US
Yuichi Wada - Tomisato, JP
Gregory L. Wojcik - Ben Lomond CA, US
Stephen Moffatt - Jersey, GB

Assignee:

Applied Material, Inc. - Santa Clara CA

International Classification:

H01L 31/075

US Classification:

257458, 257438

Abstract:

A method of fabricating a detector that involves: forming a trench in a substrate, the substrate having an upper surface; forming a first doped semiconductor layer on the substrate and in the trench; forming a second semiconductor layer on the first doped semiconductor layer and extending into the trench, the second semiconductor layer having a conductivity that is less than the conductivity of the first doped semiconductor layer; forming a third doped semiconductor layer on the second semiconductor layer and extending into the trench; removing portions of the first, second and third layers that are above a plane defined by the surface of the substrate to produce an upper, substantially planar surface and expose an upper end of the first doped semiconductor layer in the trench; forming a first electrical contact to the first semiconductor doped layer; and forming a second electrical contact to the third semiconductor doped layer.

US Patent:

7101725, Sep 5, 2006

Filed:

Jul 22, 2004

Appl. No.:

10/896754

Inventors:

Yuichi Wada - Tomisato, JP
Francisco A. Leon - Palo Alto CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438 65, 257E21529

Abstract:

A method of fabricating on optical detector, the method including providing a substrate that includes an optical waveguide formed therein and having a surface for fabricating microelectronic circuitry thereon; fabricating microelectronic circuitry on the substrate, the fabricating involving a plurality of sequential process phases; after a selected one of the plurality of sequential process phases has occurred and before the next process phase after the selected one of the plurality of process phases begins, fabricating an optical detector within the optical waveguide; and after fabricating the optical detector in the waveguide, completing the plurality of sequential process phases for fabricating the microelectronic circuitry.

US Patent:

7151881, Dec 19, 2006

Filed:

May 28, 2004

Appl. No.:

10/856127

Inventors:

Lawrence C. West - San Jose CA, US
Thomas P. Pearsall - Paris, FR
Francisco A. Leon - Palo Alto CA, US
Stephen Moffatt - Jersey, GB

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

G02B 6/10

US Classification:

385129, 385 40, 385 14, 372 64

Abstract:

An optical circuit including a semiconductor substrate; an optical waveguide formed in or on the substrate; and an optical detector formed in or on the semiconductor substrate, wherein the optical detector is aligned with the optical waveguide so as to receive an optical signal from the optical waveguide during operation, and wherein the optical detector has: a first electrode; a second electrode; and an intermediate layer between the first and second electrodes, the intermediate layer being made of a semiconductor material characterized by a conduction band, a valence band, and deep level energy states introduced between the conduction and valence bands.

US Patent:

7205624, Apr 17, 2007

Filed:

Oct 6, 2004

Appl. No.:

10/959897

Inventors:

Francisco A. Leon - Palo Alto CA, US
Lawrence C. West - San Jose CA, US

Assignee:

Applied Materials, Inc. - Santa Clara CA

International Classification:

H01L 31/00

US Classification:

257458, 257184

Abstract:

A method of fabricating a detector, the method including forming an island of detector core material on a substrate, the island having a horizontally oriented top end, a vertically oriented first sidewall, and a vertically oriented second sidewall that is opposite said first sidewall; implanting a first dopant into the first sidewall to form a first conductive region that has a top end that is part of the top end of the island; implanting a second dopant into the second sidewall to form a second conductive region that has a top end that is part of the top end of the island; fabricating a first electrical connection to the top end of the first conductive region; and fabricating a second electrical connection to the top end of the second conductive region.

US Patent:

7345307, Mar 18, 2008

Filed:

Sep 22, 2005

Appl. No.:

11/233503

Inventors:

Yaoling Pan - Union City CA, US
Francisco Leon - Palo Alto CA, US
David P. Stumbo - Belmont CA, US

Assignee:

Nanosys, Inc. - Palo Alto CA

International Classification:

H01L 29/10

US Classification:

257 57, 257 40, 257 72, 257347, 257E21007, 977762, 977763, 977764

Abstract:

The present invention is directed to thin film transistors using nanowires (or other nanostructures such as nanoribbons, nanotubes and the like) incorporated in and/or disposed proximal to conductive polymer layer(s), and production scalable methods to produce such transistors. In particular, a composite material comprising a conductive polymeric material such as polyaniline (PANI) or polypyrrole (PPY) and one or more nanowires incorporated therein is disclosed. Several nanowire-TFT fabrication methods are also provided which in one exemplary embodiment includes providing a device substrate; depositing a first conductive polymer material layer on the device substrate; defining one or more gate contact regions in the conductive polymer layer; depositing a plurality of nanowires over the conductive polymer layer at a sufficient density of nanowires to achieve an operational current level; depositing a second conductive polymer material layer on the plurality of nanowires; and forming source and drain contact regions in the second conductive polymer material layer to thereby provide electrical connectivity to the plurality of nanowires, whereby the nanowires form a channel having a length between respective ones of the source and drain regions.