Frank A Baiocchi from 732 Dorset Rd, Allentown, PA 18104, age 69, Phone: 6103360816

Senior Engineer

view source

Location:

Allentown, PA

Industry:

Semiconductors

Work:

Texas Instruments
Senior Engineer
Lsi Corporation Mar 2000 - Mar 2007
Dmts
Lsi Agere Systems Lucent Technologies Mar 2000 - Mar 2007
Principal Engineer and Failure Analysis
Lsi Corporation Mar 2000 - Mar 2007
Failure Analysis Engineer
Nokia Bell Labs 1984 - 1996
Member of Technical Staff

Education:

Harvard University 1977 - 1982
Depaul University 1973 - 1977
Bachelors, Bachelor of Science, Physics, Chemistry

Skills:

Semiconductors
Intel

Frank Baiocchi

view source

Frank Baiocchi

view source

Frank Baiocchi

view source

Us Patents

Enhanced Substrate Contact For A Semiconductor Device
view source
US Patent:

7041561, May 9, 2006
Filed:

Mar 31, 2004
Appl. No.:

10/814062
Inventors:

Frank A. Baiocchi - Allentown PA, US
Bailey R. Jones - Mohnton PA, US
Muhammed Ayman Shibib - Wyomissing PA, US
Shuming Xu - Schnecksville PA, US
Assignee:

Agere Systems Inc. - Allentown PA
International Classification:

H01L 21/336
US Classification:

438270, 438589
Abstract:

A technique for forming a semiconductor structure in a semiconductor wafer includes the steps of forming an epitaxial layer on a least a portion of a semiconductor substrate of a first conductivity type and forming at least one trench in an upper surface of the semiconductor wafer and partially into the epitaxial layer. The method further includes the step of forming at least one diffusion region between a bottom wall of the trench and the substrate, the diffusion region providing an electrical path between the bottom wall of the trench and the substrate. One or more sidewalls of the trench are doped with a first impurity of a known concentration level so as to form an electrical path between an upper surface of the epitaxial layer and the at least one diffusion region. The trench is then filled with a filler material.

Metal-Oxide-Semiconductor Device With Enhanced Source Electrode
view source
US Patent:

7126193, Oct 24, 2006
Filed:

Sep 29, 2003
Appl. No.:

10/673539
Inventors:

Frank A. Baiocchi - Allentown PA, US
Bailey R. Jones - Mohnton PA, US
Muhammed Ayman Shibib - Wyomissing PA, US
Shuming Xu - Schnecksville PA, US
Assignee:

Ciclon Semiconductor Device Corp. - Bethleham PA
International Classification:

H01L 31/119
US Classification:

257343, 257344, 257335, 257336, 257288, 257408, 257409, 257E29017, 257E29121
Abstract:

An MOS device is formed including a semiconductor layer of a first conductivity type, a first source/drain region of a second conductivity type formed in the semiconductor layer, and a second source/drain region of the second conductivity type formed in the semiconductor layer and spaced apart from the first source/drain region. A gate is formed proximate an upper surface of the semiconductor layer and at least partially between the first and second source/drain regions. The MOS device further includes at least one contact, the at least one contact including a silicide layer formed on and in electrical connection with at least a portion of the first source/drain region, the silicide layer extending laterally away from the gate. The contact further includes at least one insulating layer formed directly on the silicide layer.

Calibration Standard For Transmission Electron Microscopy
view source
US Patent:

7291849, Nov 6, 2007
Filed:

Sep 28, 2005
Appl. No.:

11/237410
Inventors:

Frank A. Baiocchi - Allentown PA, US
John Michael DeLucca - Wayne PA, US
James Thomas Cargo - Bethlehem PA, US
Assignee:

Agere Systems Inc. - Allentown PA
International Classification:

G12B 13/00
H01L 21/66
US Classification:

2504911, 2502521, 250306, 250307, 250310, 250311
Abstract:

A calibration standard includes a silicon substrate having a plurality of defined regions and a plurality of calibration marks placed on respective defined regions of the silicon substrate. Each calibration mark comprises a different calibration dimension indicator and a corresponding dimension identifier. A method for calibrating a transmission electron microscope using the standard comprises positioning the calibration standard in a viewing area of the transmission electron microscope and sequentially viewing the marks and adjusting the calibration of the microscope for each mark viewed.

Method Of Making Electronic Entities
view source
US Patent:

7724359, May 25, 2010
Filed:

May 27, 2008
Appl. No.:

12/154794
Inventors:

Ahmed Nur Amin - Fairfax VA, US
Mark Adam Bachman - Sinking Spring PA, US
Frank A. Baiocchi - Allentown PA, US
John Michael DeLucca - Wayne PA, US
John William Osenbach - Kutztown PA, US
Assignee:

Agere Systems Inc. - Allentown PA
International Classification:

G01N 21/00
US Classification:

3562373, 3562371, 3562376
Abstract:

Many electronic entities such as integrated circuits and discrete power devices have contact pads formed from successively deposited layers of nickel and a second metal such as gold. The resulting pad structure is used to make external electrical connection such as solder connection. Problems associated with failure of such connections are avoidable by inspecting the surface of the nickel layer for excessive small particle formation.

Material Removing Processes In Device Formation And The Devices Formed Thereby
view source
US Patent:

7972873, Jul 5, 2011
Filed:

Oct 27, 2008
Appl. No.:

12/290054
Inventors:

Frank A. Baiocchi - Allentown PA, US
James Thomas Cargo - Bethlehem PA, US
John Michael DeLucca - Wayne PA, US
Assignee:

Agere Systems Inc. - Allentown PA
International Classification:

H01L 21/00
H01L 21/302
H01L 31/062
US Classification:

438 8, 438708, 438745, 257394, 257E21249
Abstract:

Devices having voids are producible by employing an electrochemical corrosion process. For example, an electrically conductive region is formed to have a surrounding chemically distinct region. Such formation is possible through conventional semiconductor processing techniques such as a copper damascene process. The surrounded conducting material is configured to be in electrical communication with a charge separation structure. The electrically conducting region is contacted with a fluid electrolyte and electromagnetic radiation is made to illuminate the charge separation region to induce separation of electrons and holes. The resulting separated charges are used to drive an electrochemical corrosion process at the conductive material/electrolyte interface resulting in the removal of at least a portion of the electrically conducting material. The induced corrosion leaves a void that is useful, for example, as a highly effective dielectric in integrated circuits, functions to allow component separation such as gear separation in microelectromechanical devices or produces long cavities useful for material separation analogous to the distillation columns used in liquid chromatography.

Aluminum Bond Pads With Enhanced Wire Bond Stability
view source
US Patent:

8101871, Jan 24, 2012
Filed:

May 26, 2009
Appl. No.:

12/471982
Inventors:

Frank A. Baiocchi - Allentown PA, US
John M DeLucca - Wayne PA, US
John W. Osenbach - Kutztown PA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

H05K 1/11
US Classification:

174261, 257757, 257765, 257766, 257771, 257768
Abstract:

An electronic device bond pad includes an Al layer located over an electronic device substrate. The Al layer includes an intrinsic group 10 metal located therein.

Soldering Method And Related Device For Improved Resistance To Brittle Fracture With An Intermetallic Compound Region Coupling A Solder Mass To An Ni Layer Which Has A Low Concentration Of P, Wherein The Amount Of P In The Underlying Ni Layer Is Controlled As A Function Of The Expected Volume Of The Solder Mass
view source
US Patent:

8242378, Aug 14, 2012
Filed:

Sep 21, 2007
Appl. No.:

12/160553
Inventors:

Ahmed Amin - Allentown PA, US
Frank Baiocchi - Allentown PA, US
John Delucca - Montgomery PA, US
John Osenbach - Kutztown PA, US
Brian T. Vaccaro - Mertztown PA, US
Assignee:

Agere Systems Inc. - Allentown PA
International Classification:

H05K 1/09
B23K 31/02
B23K 1/20
US Classification:

174257, 174259, 174261, 361751, 361771, 361803
Abstract:

A lead-free solder joint is formed between a tin-silver-copper solder alloy (SAC), SACX, or other commonly used Pb-free solder alloys, and a metallization layer of a substrate. Interaction of the SAC with the metallization layer forms an intermetallic compound (IMC) that binds the solder mass to the metallization layer. The IMC region is substantially free of any phosphorous-containing layers or regions.

Dielectric Etching
view source
US Patent:

8318606, Nov 27, 2012
Filed:

Aug 25, 2009
Appl. No.:

12/546855
Inventors:

Frank Baiocchi - Allentown PA, US
David Kern - Lehighton PA, US
John DeLucca - Wayne PA, US
Assignee:

LSI Corporation - Milpitas CA
International Classification:

H01L 21/302
US Classification:

438745, 438689, 438756, 216 83, 216 96, 216 97
Abstract:

An etchant for dielectrics, such as silicon dioxide, that leaves monocrystalline silicon surface exposed by the etchant free of etch damage, such as etch pits, when the etch is done in the presence of transition metals, such as copper, tungsten, titanium, gold, etc. The etchant comprises hydrofluoric acid and a source of halide anion, such as hydrochloric acid or a metal-halide. The etchant is useful in microelectromechanical system device fabrication and in deprocessing integrated circuits or the like.